1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_SH_SMC37C93X_H
3#define __ASM_SH_SMC37C93X_H
4
5/*
6 * linux/include/asm-sh/smc37c93x.h
7 *
8 * Copyright (C) 2000  Kazumoto Kojima
9 *
10 * SMSC 37C93x Super IO Chip support
11 */
12
13/* Default base I/O address */
14#define FDC_PRIMARY_BASE	0x3f0
15#define IDE1_PRIMARY_BASE	0x1f0
16#define IDE1_SECONDARY_BASE	0x170
17#define PARPORT_PRIMARY_BASE	0x378
18#define COM1_PRIMARY_BASE	0x2f8
19#define COM2_PRIMARY_BASE	0x3f8
20#define RTC_PRIMARY_BASE	0x070
21#define KBC_PRIMARY_BASE	0x060
22#define AUXIO_PRIMARY_BASE	0x000	/* XXX */
23
24/* Logical device number */
25#define LDN_FDC			0
26#define LDN_IDE1		1
27#define LDN_IDE2		2
28#define LDN_PARPORT		3
29#define LDN_COM1		4
30#define LDN_COM2		5
31#define LDN_RTC			6
32#define LDN_KBC			7
33#define LDN_AUXIO		8
34
35/* Configuration port and key */
36#define CONFIG_PORT		0x3f0
37#define INDEX_PORT		CONFIG_PORT
38#define DATA_PORT		0x3f1
39#define CONFIG_ENTER		0x55
40#define CONFIG_EXIT		0xaa
41
42/* Configuration index */
43#define CURRENT_LDN_INDEX	0x07
44#define POWER_CONTROL_INDEX	0x22
45#define ACTIVATE_INDEX		0x30
46#define IO_BASE_HI_INDEX	0x60
47#define IO_BASE_LO_INDEX	0x61
48#define IRQ_SELECT_INDEX	0x70
49#define DMA_SELECT_INDEX	0x74
50
51#define GPIO46_INDEX		0xc6
52#define GPIO47_INDEX		0xc7
53
54/* UART stuff. Only for debugging.  */
55/* UART Register */
56
57#define UART_RBR	0x0	/* Receiver Buffer Register (Read Only) */
58#define UART_THR	0x0	/* Transmitter Holding Register (Write Only) */
59#define UART_IER	0x2	/* Interrupt Enable Register */
60#define UART_IIR	0x4	/* Interrupt Ident Register (Read Only) */
61#define UART_FCR	0x4	/* FIFO Control Register (Write Only) */
62#define UART_LCR	0x6	/* Line Control Register */
63#define UART_MCR	0x8	/* MODEM Control Register */
64#define UART_LSR	0xa	/* Line Status Register */
65#define UART_MSR	0xc	/* MODEM Status Register */
66#define UART_SCR	0xe	/* Scratch Register */
67#define UART_DLL	0x0	/* Divisor Latch (LS) */
68#define UART_DLM	0x2	/* Divisor Latch (MS) */
69
70#ifndef __ASSEMBLY__
71typedef struct uart_reg {
72	volatile __u16 rbr;
73	volatile __u16 ier;
74	volatile __u16 iir;
75	volatile __u16 lcr;
76	volatile __u16 mcr;
77	volatile __u16 lsr;
78	volatile __u16 msr;
79	volatile __u16 scr;
80} uart_reg;
81#endif /* ! __ASSEMBLY__ */
82
83/* Alias for Write Only Register */
84
85#define thr	rbr
86#define tcr	iir
87
88/* Alias for Divisor Latch Register */
89
90#define dll	rbr
91#define dlm	ier
92#define fcr	iir
93
94/* Interrupt Enable Register */
95
96#define IER_ERDAI	0x0100	/* Enable Received Data Available Interrupt */
97#define IER_ETHREI	0x0200	/* Enable Transmitter Holding Register Empty Interrupt */
98#define IER_ELSI	0x0400	/* Enable Receiver Line Status Interrupt */
99#define IER_EMSI	0x0800	/* Enable MODEM Status Interrupt */
100
101/* Interrupt Ident Register */
102
103#define IIR_IP		0x0100	/* "0" if Interrupt Pending */
104#define IIR_IIB0	0x0200	/* Interrupt ID Bit 0 */
105#define IIR_IIB1	0x0400	/* Interrupt ID Bit 1 */
106#define IIR_IIB2	0x0800	/* Interrupt ID Bit 2 */
107#define IIR_FIFO	0xc000	/* FIFOs enabled */
108
109/* FIFO Control Register */
110
111#define FCR_FEN		0x0100	/* FIFO enable */
112#define FCR_RFRES	0x0200	/* Receiver FIFO reset */
113#define FCR_TFRES	0x0400	/* Transmitter FIFO reset */
114#define FCR_DMA		0x0800	/* DMA mode select */
115#define FCR_RTL		0x4000	/* Receiver trigger (LSB) */
116#define FCR_RTM		0x8000	/* Receiver trigger (MSB) */
117
118/* Line Control Register */
119
120#define LCR_WLS0	0x0100	/* Word Length Select Bit 0 */
121#define LCR_WLS1	0x0200	/* Word Length Select Bit 1 */
122#define LCR_STB		0x0400	/* Number of Stop Bits */
123#define LCR_PEN		0x0800	/* Parity Enable */
124#define LCR_EPS		0x1000	/* Even Parity Select */
125#define LCR_SP		0x2000	/* Stick Parity */
126#define LCR_SB		0x4000	/* Set Break */
127#define LCR_DLAB	0x8000	/* Divisor Latch Access Bit */
128
129/* MODEM Control Register */
130
131#define MCR_DTR		0x0100	/* Data Terminal Ready */
132#define MCR_RTS		0x0200	/* Request to Send */
133#define MCR_OUT1	0x0400	/* Out 1 */
134#define MCR_IRQEN	0x0800	/* IRQ Enable */
135#define MCR_LOOP	0x1000	/* Loop */
136
137/* Line Status Register */
138
139#define LSR_DR		0x0100	/* Data Ready */
140#define LSR_OE		0x0200	/* Overrun Error */
141#define LSR_PE		0x0400	/* Parity Error */
142#define LSR_FE		0x0800	/* Framing Error */
143#define LSR_BI		0x1000	/* Break Interrupt */
144#define LSR_THRE	0x2000	/* Transmitter Holding Register Empty */
145#define LSR_TEMT	0x4000	/* Transmitter Empty */
146#define LSR_FIFOE	0x8000	/* Receiver FIFO error */
147
148/* MODEM Status Register */
149
150#define MSR_DCTS	0x0100	/* Delta Clear to Send */
151#define MSR_DDSR	0x0200	/* Delta Data Set Ready */
152#define MSR_TERI	0x0400	/* Trailing Edge Ring Indicator */
153#define MSR_DDCD	0x0800	/* Delta Data Carrier Detect */
154#define MSR_CTS		0x1000	/* Clear to Send */
155#define MSR_DSR		0x2000	/* Data Set Ready */
156#define MSR_RI		0x4000	/* Ring Indicator */
157#define MSR_DCD		0x8000	/* Data Carrier Detect */
158
159/* Baud Rate Divisor */
160
161#define UART_CLK	(1843200)	/* 1.8432 MHz */
162#define UART_BAUD(x)	(UART_CLK / (16 * (x)))
163
164/* RTC register definition */
165#define RTC_SECONDS             0
166#define RTC_SECONDS_ALARM       1
167#define RTC_MINUTES             2
168#define RTC_MINUTES_ALARM       3
169#define RTC_HOURS               4
170#define RTC_HOURS_ALARM         5
171#define RTC_DAY_OF_WEEK         6
172#define RTC_DAY_OF_MONTH        7
173#define RTC_MONTH               8
174#define RTC_YEAR                9
175#define RTC_FREQ_SELECT		10
176# define RTC_UIP 0x80
177# define RTC_DIV_CTL 0x70
178/* This RTC can work under 32.768KHz clock only.  */
179# define RTC_OSC_ENABLE 0x20
180# define RTC_OSC_DISABLE 0x00
181#define RTC_CONTROL     	11
182# define RTC_SET 0x80
183# define RTC_PIE 0x40
184# define RTC_AIE 0x20
185# define RTC_UIE 0x10
186# define RTC_SQWE 0x08
187# define RTC_DM_BINARY 0x04
188# define RTC_24H 0x02
189# define RTC_DST_EN 0x01
190
191#endif  /* __ASM_SH_SMC37C93X_H */
192