1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_S390_PCI_CLP_H
3#define _ASM_S390_PCI_CLP_H
4
5#include <asm/clp.h>
6
7/*
8 * Call Logical Processor - Command Codes
9 */
10#define CLP_SLPC		0x0001
11#define CLP_LIST_PCI		0x0002
12#define CLP_QUERY_PCI_FN	0x0003
13#define CLP_QUERY_PCI_FNGRP	0x0004
14#define CLP_SET_PCI_FN		0x0005
15
16/* PCI function handle list entry */
17struct clp_fh_list_entry {
18	u16 device_id;
19	u16 vendor_id;
20	u32 config_state :  1;
21	u32		 : 31;
22	u32 fid;		/* PCI function id */
23	u32 fh;			/* PCI function handle */
24} __packed;
25
26#define CLP_RC_SETPCIFN_FH	0x0101	/* Invalid PCI fn handle */
27#define CLP_RC_SETPCIFN_FHOP	0x0102	/* Fn handle not valid for op */
28#define CLP_RC_SETPCIFN_DMAAS	0x0103	/* Invalid DMA addr space */
29#define CLP_RC_SETPCIFN_RES	0x0104	/* Insufficient resources */
30#define CLP_RC_SETPCIFN_ALRDY	0x0105	/* Fn already in requested state */
31#define CLP_RC_SETPCIFN_ERR	0x0106	/* Fn in permanent error state */
32#define CLP_RC_SETPCIFN_RECPND	0x0107	/* Error recovery pending */
33#define CLP_RC_SETPCIFN_BUSY	0x0108	/* Fn busy */
34#define CLP_RC_LISTPCI_BADRT	0x010a	/* Resume token not recognized */
35#define CLP_RC_QUERYPCIFG_PFGID	0x010b	/* Unrecognized PFGID */
36
37/* request or response block header length */
38#define LIST_PCI_HDR_LEN	32
39
40/* Number of function handles fitting in response block */
41#define CLP_FH_LIST_NR_ENTRIES				\
42	((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)		\
43		/ sizeof(struct clp_fh_list_entry))
44
45#define CLP_SET_ENABLE_PCI_FN	0	/* Yes, 0 enables it */
46#define CLP_SET_DISABLE_PCI_FN	1	/* Yes, 1 disables it */
47#define CLP_SET_ENABLE_MIO	2
48#define CLP_SET_DISABLE_MIO	3
49
50#define CLP_UTIL_STR_LEN	64
51#define CLP_PFIP_NR_SEGMENTS	4
52
53/* PCI function type numbers */
54#define PCI_FUNC_TYPE_ISM	0x5	/* ISM device */
55
56extern bool zpci_unique_uid;
57
58struct clp_rsp_slpc_pci {
59	struct clp_rsp_hdr hdr;
60	u32 reserved2[4];
61	u32 lpif[8];
62	u32 reserved3[4];
63	u32 vwb		:  1;
64	u32		:  1;
65	u32 mio_wb	:  6;
66	u32		: 24;
67	u32 reserved5[3];
68	u32 lpic[8];
69} __packed;
70
71/* List PCI functions request */
72struct clp_req_list_pci {
73	struct clp_req_hdr hdr;
74	u64 resume_token;
75	u64 reserved2;
76} __packed;
77
78/* List PCI functions response */
79struct clp_rsp_list_pci {
80	struct clp_rsp_hdr hdr;
81	u64 resume_token;
82	u32 reserved2;
83	u16 max_fn;
84	u8			: 7;
85	u8 uid_checking		: 1;
86	u8 entry_size;
87	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
88} __packed;
89
90struct mio_info {
91	u32 valid : 6;
92	u32 : 26;
93	u32 : 32;
94	struct {
95		u64 wb;
96		u64 wt;
97	} addr[PCI_STD_NUM_BARS];
98	u32 reserved[6];
99} __packed;
100
101/* Query PCI function request */
102struct clp_req_query_pci {
103	struct clp_req_hdr hdr;
104	u32 fh;				/* function handle */
105	u32 reserved2;
106	u64 reserved3;
107} __packed;
108
109/* Query PCI function response */
110struct clp_rsp_query_pci {
111	struct clp_rsp_hdr hdr;
112	u16 vfn;			/* virtual fn number */
113	u16			:  3;
114	u16 rid_avail		:  1;
115	u16 is_physfn		:  1;
116	u16 reserved1		:  1;
117	u16 mio_addr_avail	:  1;
118	u16 util_str_avail	:  1;	/* utility string available? */
119	u16 pfgid		:  8;	/* pci function group id */
120	u32 fid;			/* pci function id */
121	u8 bar_size[PCI_STD_NUM_BARS];
122	u16 pchid;
123	__le32 bar[PCI_STD_NUM_BARS];
124	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
125	u16			: 12;
126	u16 port		:  4;
127	u8 fmb_len;
128	u8 pft;				/* pci function type */
129	u64 sdma;			/* start dma as */
130	u64 edma;			/* end dma as */
131#define ZPCI_RID_MASK_DEVFN 0x00ff
132	u16 rid;			/* BUS/DEVFN PCI address */
133	u16 reserved0;
134	u32 reserved[10];
135	u32 uid;			/* user defined id */
136	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
137	u32 reserved2[16];
138	struct mio_info mio;
139} __packed;
140
141/* Query PCI function group request */
142struct clp_req_query_pci_grp {
143	struct clp_req_hdr hdr;
144	u32 reserved2		: 24;
145	u32 pfgid		:  8;	/* function group id */
146	u32 reserved3;
147	u64 reserved4;
148} __packed;
149
150/* Query PCI function group response */
151struct clp_rsp_query_pci_grp {
152	struct clp_rsp_hdr hdr;
153	u16			:  4;
154	u16 noi			: 12;	/* number of interrupts */
155	u8 version;
156	u8			:  6;
157	u8 frame		:  1;
158	u8 refresh		:  1;	/* TLB refresh mode */
159	u16			:  3;
160	u16 maxstbl		: 13;	/* Maximum store block size */
161	u16 mui;
162	u8 dtsm;			/* Supported DT mask */
163	u8 reserved3;
164	u16 maxfaal;
165	u16			:  4;
166	u16 dnoi		: 12;
167	u16 maxcpu;
168	u64 dasm;			/* dma address space mask */
169	u64 msia;			/* MSI address */
170	u64 reserved4;
171	u64 reserved5;
172} __packed;
173
174/* Set PCI function request */
175struct clp_req_set_pci {
176	struct clp_req_hdr hdr;
177	u32 fh;				/* function handle */
178	u16 reserved2;
179	u8 oc;				/* operation controls */
180	u8 ndas;			/* number of dma spaces */
181	u32 reserved3;
182	u32 gisa;			/* GISA designation */
183} __packed;
184
185/* Set PCI function response */
186struct clp_rsp_set_pci {
187	struct clp_rsp_hdr hdr;
188	u32 fh;				/* function handle */
189	u32 reserved1;
190	u64 reserved2;
191	struct mio_info mio;
192} __packed;
193
194/* Combined request/response block structures used by clp insn */
195struct clp_req_rsp_slpc_pci {
196	struct clp_req_slpc request;
197	struct clp_rsp_slpc_pci response;
198} __packed;
199
200struct clp_req_rsp_list_pci {
201	struct clp_req_list_pci request;
202	struct clp_rsp_list_pci response;
203} __packed;
204
205struct clp_req_rsp_set_pci {
206	struct clp_req_set_pci request;
207	struct clp_rsp_set_pci response;
208} __packed;
209
210struct clp_req_rsp_query_pci {
211	struct clp_req_query_pci request;
212	struct clp_rsp_query_pci response;
213} __packed;
214
215struct clp_req_rsp_query_pci_grp {
216	struct clp_req_query_pci_grp request;
217	struct clp_rsp_query_pci_grp response;
218} __packed;
219
220#endif
221