1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015 Regents of the University of California 4 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 */ 6 7#ifndef _ASM_RISCV_SBI_H 8#define _ASM_RISCV_SBI_H 9 10#include <linux/types.h> 11#include <linux/cpumask.h> 12 13#ifdef CONFIG_RISCV_SBI 14enum sbi_ext_id { 15#ifdef CONFIG_RISCV_SBI_V01 16 SBI_EXT_0_1_SET_TIMER = 0x0, 17 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, 18 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, 19 SBI_EXT_0_1_CLEAR_IPI = 0x3, 20 SBI_EXT_0_1_SEND_IPI = 0x4, 21 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, 22 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, 23 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, 24 SBI_EXT_0_1_SHUTDOWN = 0x8, 25#endif 26 SBI_EXT_BASE = 0x10, 27 SBI_EXT_TIME = 0x54494D45, 28 SBI_EXT_IPI = 0x735049, 29 SBI_EXT_RFENCE = 0x52464E43, 30 SBI_EXT_HSM = 0x48534D, 31 SBI_EXT_SRST = 0x53525354, 32 SBI_EXT_SUSP = 0x53555350, 33 SBI_EXT_PMU = 0x504D55, 34 SBI_EXT_DBCN = 0x4442434E, 35 SBI_EXT_STA = 0x535441, 36 37 /* Experimentals extensions must lie within this range */ 38 SBI_EXT_EXPERIMENTAL_START = 0x08000000, 39 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF, 40 41 /* Vendor extensions must lie within this range */ 42 SBI_EXT_VENDOR_START = 0x09000000, 43 SBI_EXT_VENDOR_END = 0x09FFFFFF, 44}; 45 46enum sbi_ext_base_fid { 47 SBI_EXT_BASE_GET_SPEC_VERSION = 0, 48 SBI_EXT_BASE_GET_IMP_ID, 49 SBI_EXT_BASE_GET_IMP_VERSION, 50 SBI_EXT_BASE_PROBE_EXT, 51 SBI_EXT_BASE_GET_MVENDORID, 52 SBI_EXT_BASE_GET_MARCHID, 53 SBI_EXT_BASE_GET_MIMPID, 54}; 55 56enum sbi_ext_time_fid { 57 SBI_EXT_TIME_SET_TIMER = 0, 58}; 59 60enum sbi_ext_ipi_fid { 61 SBI_EXT_IPI_SEND_IPI = 0, 62}; 63 64enum sbi_ext_rfence_fid { 65 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, 66 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, 67 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, 68 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, 69 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, 70 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, 71 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, 72}; 73 74enum sbi_ext_hsm_fid { 75 SBI_EXT_HSM_HART_START = 0, 76 SBI_EXT_HSM_HART_STOP, 77 SBI_EXT_HSM_HART_STATUS, 78 SBI_EXT_HSM_HART_SUSPEND, 79}; 80 81enum sbi_hsm_hart_state { 82 SBI_HSM_STATE_STARTED = 0, 83 SBI_HSM_STATE_STOPPED, 84 SBI_HSM_STATE_START_PENDING, 85 SBI_HSM_STATE_STOP_PENDING, 86 SBI_HSM_STATE_SUSPENDED, 87 SBI_HSM_STATE_SUSPEND_PENDING, 88 SBI_HSM_STATE_RESUME_PENDING, 89}; 90 91#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff 92#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 93#define SBI_HSM_SUSP_PLAT_BASE 0x10000000 94 95#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 96#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE 97#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK 98#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT 99#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ 100 SBI_HSM_SUSP_PLAT_BASE) 101#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ 102 SBI_HSM_SUSP_BASE_MASK) 103 104enum sbi_ext_srst_fid { 105 SBI_EXT_SRST_RESET = 0, 106}; 107 108enum sbi_srst_reset_type { 109 SBI_SRST_RESET_TYPE_SHUTDOWN = 0, 110 SBI_SRST_RESET_TYPE_COLD_REBOOT, 111 SBI_SRST_RESET_TYPE_WARM_REBOOT, 112}; 113 114enum sbi_srst_reset_reason { 115 SBI_SRST_RESET_REASON_NONE = 0, 116 SBI_SRST_RESET_REASON_SYS_FAILURE, 117}; 118 119enum sbi_ext_susp_fid { 120 SBI_EXT_SUSP_SYSTEM_SUSPEND = 0, 121}; 122 123enum sbi_ext_susp_sleep_type { 124 SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0, 125}; 126 127enum sbi_ext_pmu_fid { 128 SBI_EXT_PMU_NUM_COUNTERS = 0, 129 SBI_EXT_PMU_COUNTER_GET_INFO, 130 SBI_EXT_PMU_COUNTER_CFG_MATCH, 131 SBI_EXT_PMU_COUNTER_START, 132 SBI_EXT_PMU_COUNTER_STOP, 133 SBI_EXT_PMU_COUNTER_FW_READ, 134}; 135 136union sbi_pmu_ctr_info { 137 unsigned long value; 138 struct { 139 unsigned long csr:12; 140 unsigned long width:6; 141#if __riscv_xlen == 32 142 unsigned long reserved:13; 143#else 144 unsigned long reserved:45; 145#endif 146 unsigned long type:1; 147 }; 148}; 149 150#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) 151#define RISCV_PMU_RAW_EVENT_IDX 0x20000 152 153/** General pmu event codes specified in SBI PMU extension */ 154enum sbi_pmu_hw_generic_events_t { 155 SBI_PMU_HW_NO_EVENT = 0, 156 SBI_PMU_HW_CPU_CYCLES = 1, 157 SBI_PMU_HW_INSTRUCTIONS = 2, 158 SBI_PMU_HW_CACHE_REFERENCES = 3, 159 SBI_PMU_HW_CACHE_MISSES = 4, 160 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, 161 SBI_PMU_HW_BRANCH_MISSES = 6, 162 SBI_PMU_HW_BUS_CYCLES = 7, 163 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, 164 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, 165 SBI_PMU_HW_REF_CPU_CYCLES = 10, 166 167 SBI_PMU_HW_GENERAL_MAX, 168}; 169 170/** 171 * Special "firmware" events provided by the firmware, even if the hardware 172 * does not support performance events. These events are encoded as a raw 173 * event type in Linux kernel perf framework. 174 */ 175enum sbi_pmu_fw_generic_events_t { 176 SBI_PMU_FW_MISALIGNED_LOAD = 0, 177 SBI_PMU_FW_MISALIGNED_STORE = 1, 178 SBI_PMU_FW_ACCESS_LOAD = 2, 179 SBI_PMU_FW_ACCESS_STORE = 3, 180 SBI_PMU_FW_ILLEGAL_INSN = 4, 181 SBI_PMU_FW_SET_TIMER = 5, 182 SBI_PMU_FW_IPI_SENT = 6, 183 SBI_PMU_FW_IPI_RCVD = 7, 184 SBI_PMU_FW_FENCE_I_SENT = 8, 185 SBI_PMU_FW_FENCE_I_RCVD = 9, 186 SBI_PMU_FW_SFENCE_VMA_SENT = 10, 187 SBI_PMU_FW_SFENCE_VMA_RCVD = 11, 188 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, 189 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, 190 191 SBI_PMU_FW_HFENCE_GVMA_SENT = 14, 192 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, 193 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, 194 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, 195 196 SBI_PMU_FW_HFENCE_VVMA_SENT = 18, 197 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, 198 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, 199 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, 200 SBI_PMU_FW_MAX, 201}; 202 203/* SBI PMU event types */ 204enum sbi_pmu_event_type { 205 SBI_PMU_EVENT_TYPE_HW = 0x0, 206 SBI_PMU_EVENT_TYPE_CACHE = 0x1, 207 SBI_PMU_EVENT_TYPE_RAW = 0x2, 208 SBI_PMU_EVENT_TYPE_FW = 0xf, 209}; 210 211/* SBI PMU event types */ 212enum sbi_pmu_ctr_type { 213 SBI_PMU_CTR_TYPE_HW = 0x0, 214 SBI_PMU_CTR_TYPE_FW, 215}; 216 217/* Helper macros to decode event idx */ 218#define SBI_PMU_EVENT_IDX_OFFSET 20 219#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF 220#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF 221#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 222#define SBI_PMU_EVENT_RAW_IDX 0x20000 223#define SBI_PMU_FIXED_CTR_MASK 0x07 224 225#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 226#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 227#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 228 229#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3 230#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1 231 232#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF 233 234/* Flags defined for config matching function */ 235#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) 236#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) 237#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) 238#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) 239#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) 240#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) 241#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) 242#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) 243 244/* Flags defined for counter start function */ 245#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) 246 247/* Flags defined for counter stop function */ 248#define SBI_PMU_STOP_FLAG_RESET (1 << 0) 249 250enum sbi_ext_dbcn_fid { 251 SBI_EXT_DBCN_CONSOLE_WRITE = 0, 252 SBI_EXT_DBCN_CONSOLE_READ = 1, 253 SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, 254}; 255 256/* SBI STA (steal-time accounting) extension */ 257enum sbi_ext_sta_fid { 258 SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0, 259}; 260 261struct sbi_sta_struct { 262 __le32 sequence; 263 __le32 flags; 264 __le64 steal; 265 u8 preempted; 266 u8 pad[47]; 267} __packed; 268 269#define SBI_STA_SHMEM_DISABLE -1 270 271/* SBI spec version fields */ 272#define SBI_SPEC_VERSION_DEFAULT 0x1 273#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 274#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 275#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 276 277/* SBI return error codes */ 278#define SBI_SUCCESS 0 279#define SBI_ERR_FAILURE -1 280#define SBI_ERR_NOT_SUPPORTED -2 281#define SBI_ERR_INVALID_PARAM -3 282#define SBI_ERR_DENIED -4 283#define SBI_ERR_INVALID_ADDRESS -5 284#define SBI_ERR_ALREADY_AVAILABLE -6 285#define SBI_ERR_ALREADY_STARTED -7 286#define SBI_ERR_ALREADY_STOPPED -8 287 288extern unsigned long sbi_spec_version; 289struct sbiret { 290 long error; 291 long value; 292}; 293 294void sbi_init(void); 295struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 296 unsigned long arg1, unsigned long arg2, 297 unsigned long arg3, unsigned long arg4, 298 unsigned long arg5); 299 300#ifdef CONFIG_RISCV_SBI_V01 301void sbi_console_putchar(int ch); 302int sbi_console_getchar(void); 303#else 304static inline void sbi_console_putchar(int ch) { } 305static inline int sbi_console_getchar(void) { return -ENOENT; } 306#endif 307long sbi_get_mvendorid(void); 308long sbi_get_marchid(void); 309long sbi_get_mimpid(void); 310void sbi_set_timer(uint64_t stime_value); 311void sbi_shutdown(void); 312void sbi_send_ipi(unsigned int cpu); 313int sbi_remote_fence_i(const struct cpumask *cpu_mask); 314 315int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask, 316 unsigned long start, 317 unsigned long size, 318 unsigned long asid); 319int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask, 320 unsigned long start, 321 unsigned long size); 322int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask, 323 unsigned long start, 324 unsigned long size, 325 unsigned long vmid); 326int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask, 327 unsigned long start, 328 unsigned long size); 329int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, 330 unsigned long start, 331 unsigned long size, 332 unsigned long asid); 333long sbi_probe_extension(int ext); 334 335/* Check if current SBI specification version is 0.1 or not */ 336static inline int sbi_spec_is_0_1(void) 337{ 338 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0; 339} 340 341/* Get the major version of SBI */ 342static inline unsigned long sbi_major_version(void) 343{ 344 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) & 345 SBI_SPEC_VERSION_MAJOR_MASK; 346} 347 348/* Get the minor version of SBI */ 349static inline unsigned long sbi_minor_version(void) 350{ 351 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; 352} 353 354/* Make SBI version */ 355static inline unsigned long sbi_mk_version(unsigned long major, 356 unsigned long minor) 357{ 358 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << 359 SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; 360} 361 362int sbi_err_map_linux_errno(int err); 363 364extern bool sbi_debug_console_available; 365int sbi_debug_console_write(const char *bytes, unsigned int num_bytes); 366int sbi_debug_console_read(char *bytes, unsigned int num_bytes); 367 368#else /* CONFIG_RISCV_SBI */ 369static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } 370static inline void sbi_init(void) {} 371#endif /* CONFIG_RISCV_SBI */ 372 373unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 374unsigned long riscv_cached_marchid(unsigned int cpu_id); 375unsigned long riscv_cached_mimpid(unsigned int cpu_id); 376 377#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) 378void sbi_ipi_init(void); 379#else 380static inline void sbi_ipi_init(void) { } 381#endif 382 383#endif /* _ASM_RISCV_SBI_H */ 384