1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 can0_pins: can0-pins { 57 pins = "PB2", "PB3"; 58 function = "can0"; 59 }; 60 61 /omit-if-no-ref/ 62 can1_pins: can1-pins { 63 pins = "PB4", "PB5"; 64 function = "can1"; 65 }; 66 67 /omit-if-no-ref/ 68 clk_pg11_pin: clk-pg11-pin { 69 pins = "PG11"; 70 function = "clk"; 71 }; 72 73 /omit-if-no-ref/ 74 dsi_4lane_pins: dsi-4lane-pins { 75 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 76 "PD6", "PD7", "PD8", "PD9"; 77 drive-strength = <30>; 78 function = "dsi"; 79 }; 80 81 /omit-if-no-ref/ 82 lcd_rgb666_pins: lcd-rgb666-pins { 83 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 84 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 85 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 86 "PD18", "PD19", "PD20", "PD21"; 87 function = "lcd0"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc0_pins: mmc0-pins { 92 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 93 function = "mmc0"; 94 }; 95 96 /omit-if-no-ref/ 97 mmc1_pins: mmc1-pins { 98 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 99 function = "mmc1"; 100 }; 101 102 /omit-if-no-ref/ 103 mmc2_pins: mmc2-pins { 104 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 105 function = "mmc2"; 106 }; 107 108 /omit-if-no-ref/ 109 rgmii_pe_pins: rgmii-pe-pins { 110 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 111 "PE5", "PE6", "PE7", "PE8", "PE9", 112 "PE11", "PE12", "PE13", "PE14", "PE15"; 113 function = "emac"; 114 }; 115 116 /omit-if-no-ref/ 117 rmii_pe_pins: rmii-pe-pins { 118 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 119 "PE5", "PE6", "PE7", "PE8", "PE9"; 120 function = "emac"; 121 }; 122 123 /omit-if-no-ref/ 124 spi0_pins: spi0-pins { 125 pins = "PC2", "PC3", "PC4", "PC5"; 126 function = "spi0"; 127 }; 128 129 /omit-if-no-ref/ 130 uart1_pg6_pins: uart1-pg6-pins { 131 pins = "PG6", "PG7"; 132 function = "uart1"; 133 }; 134 135 /omit-if-no-ref/ 136 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 137 pins = "PG8", "PG9"; 138 function = "uart1"; 139 }; 140 141 /omit-if-no-ref/ 142 uart3_pb_pins: uart3-pb-pins { 143 pins = "PB6", "PB7"; 144 function = "uart3"; 145 }; 146 }; 147 148 ccu: clock-controller@2001000 { 149 compatible = "allwinner,sun20i-d1-ccu"; 150 reg = <0x2001000 0x1000>; 151 clocks = <&dcxo>, 152 <&rtc CLK_OSC32K>, 153 <&rtc CLK_IOSC>; 154 clock-names = "hosc", "losc", "iosc"; 155 #clock-cells = <1>; 156 #reset-cells = <1>; 157 }; 158 159 gpadc: adc@2009000 { 160 compatible = "allwinner,sun20i-d1-gpadc"; 161 reg = <0x2009000 0x400>; 162 clocks = <&ccu CLK_BUS_GPADC>; 163 resets = <&ccu RST_BUS_GPADC>; 164 interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; 165 status = "disabled"; 166 #io-channel-cells = <1>; 167 }; 168 169 dmic: dmic@2031000 { 170 compatible = "allwinner,sun20i-d1-dmic", 171 "allwinner,sun50i-h6-dmic"; 172 reg = <0x2031000 0x400>; 173 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&ccu CLK_BUS_DMIC>, 175 <&ccu CLK_DMIC>; 176 clock-names = "bus", "mod"; 177 resets = <&ccu RST_BUS_DMIC>; 178 dmas = <&dma 8>; 179 dma-names = "rx"; 180 status = "disabled"; 181 #sound-dai-cells = <0>; 182 }; 183 184 i2s1: i2s@2033000 { 185 compatible = "allwinner,sun20i-d1-i2s", 186 "allwinner,sun50i-r329-i2s"; 187 reg = <0x2033000 0x1000>; 188 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&ccu CLK_BUS_I2S1>, 190 <&ccu CLK_I2S1>; 191 clock-names = "apb", "mod"; 192 resets = <&ccu RST_BUS_I2S1>; 193 dmas = <&dma 4>, <&dma 4>; 194 dma-names = "rx", "tx"; 195 status = "disabled"; 196 #sound-dai-cells = <0>; 197 }; 198 199 i2s2: i2s@2034000 { 200 compatible = "allwinner,sun20i-d1-i2s", 201 "allwinner,sun50i-r329-i2s"; 202 reg = <0x2034000 0x1000>; 203 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&ccu CLK_BUS_I2S2>, 205 <&ccu CLK_I2S2>; 206 clock-names = "apb", "mod"; 207 resets = <&ccu RST_BUS_I2S2>; 208 dmas = <&dma 5>, <&dma 5>; 209 dma-names = "rx", "tx"; 210 status = "disabled"; 211 #sound-dai-cells = <0>; 212 }; 213 214 timer: timer@2050000 { 215 compatible = "allwinner,sun20i-d1-timer", 216 "allwinner,sun8i-a23-timer"; 217 reg = <0x2050000 0xa0>; 218 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 219 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&dcxo>; 221 }; 222 223 wdt: watchdog@20500a0 { 224 compatible = "allwinner,sun20i-d1-wdt-reset", 225 "allwinner,sun20i-d1-wdt"; 226 reg = <0x20500a0 0x20>; 227 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 229 clock-names = "hosc", "losc"; 230 status = "reserved"; 231 }; 232 233 uart0: serial@2500000 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x2500000 0x400>; 236 reg-io-width = <4>; 237 reg-shift = <2>; 238 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&ccu CLK_BUS_UART0>; 240 resets = <&ccu RST_BUS_UART0>; 241 dmas = <&dma 14>, <&dma 14>; 242 dma-names = "tx", "rx"; 243 status = "disabled"; 244 }; 245 246 uart1: serial@2500400 { 247 compatible = "snps,dw-apb-uart"; 248 reg = <0x2500400 0x400>; 249 reg-io-width = <4>; 250 reg-shift = <2>; 251 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&ccu CLK_BUS_UART1>; 253 resets = <&ccu RST_BUS_UART1>; 254 dmas = <&dma 15>, <&dma 15>; 255 dma-names = "tx", "rx"; 256 status = "disabled"; 257 }; 258 259 uart2: serial@2500800 { 260 compatible = "snps,dw-apb-uart"; 261 reg = <0x2500800 0x400>; 262 reg-io-width = <4>; 263 reg-shift = <2>; 264 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&ccu CLK_BUS_UART2>; 266 resets = <&ccu RST_BUS_UART2>; 267 dmas = <&dma 16>, <&dma 16>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 uart3: serial@2500c00 { 273 compatible = "snps,dw-apb-uart"; 274 reg = <0x2500c00 0x400>; 275 reg-io-width = <4>; 276 reg-shift = <2>; 277 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&ccu CLK_BUS_UART3>; 279 resets = <&ccu RST_BUS_UART3>; 280 dmas = <&dma 17>, <&dma 17>; 281 dma-names = "tx", "rx"; 282 status = "disabled"; 283 }; 284 285 uart4: serial@2501000 { 286 compatible = "snps,dw-apb-uart"; 287 reg = <0x2501000 0x400>; 288 reg-io-width = <4>; 289 reg-shift = <2>; 290 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&ccu CLK_BUS_UART4>; 292 resets = <&ccu RST_BUS_UART4>; 293 dmas = <&dma 18>, <&dma 18>; 294 dma-names = "tx", "rx"; 295 status = "disabled"; 296 }; 297 298 uart5: serial@2501400 { 299 compatible = "snps,dw-apb-uart"; 300 reg = <0x2501400 0x400>; 301 reg-io-width = <4>; 302 reg-shift = <2>; 303 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&ccu CLK_BUS_UART5>; 305 resets = <&ccu RST_BUS_UART5>; 306 dmas = <&dma 19>, <&dma 19>; 307 dma-names = "tx", "rx"; 308 status = "disabled"; 309 }; 310 311 i2c0: i2c@2502000 { 312 compatible = "allwinner,sun20i-d1-i2c", 313 "allwinner,sun8i-v536-i2c", 314 "allwinner,sun6i-a31-i2c"; 315 reg = <0x2502000 0x400>; 316 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&ccu CLK_BUS_I2C0>; 318 resets = <&ccu RST_BUS_I2C0>; 319 dmas = <&dma 43>, <&dma 43>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 326 i2c1: i2c@2502400 { 327 compatible = "allwinner,sun20i-d1-i2c", 328 "allwinner,sun8i-v536-i2c", 329 "allwinner,sun6i-a31-i2c"; 330 reg = <0x2502400 0x400>; 331 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ccu CLK_BUS_I2C1>; 333 resets = <&ccu RST_BUS_I2C1>; 334 dmas = <&dma 44>, <&dma 44>; 335 dma-names = "rx", "tx"; 336 status = "disabled"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 }; 340 341 i2c2: i2c@2502800 { 342 compatible = "allwinner,sun20i-d1-i2c", 343 "allwinner,sun8i-v536-i2c", 344 "allwinner,sun6i-a31-i2c"; 345 reg = <0x2502800 0x400>; 346 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&ccu CLK_BUS_I2C2>; 348 resets = <&ccu RST_BUS_I2C2>; 349 dmas = <&dma 45>, <&dma 45>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 356 i2c3: i2c@2502c00 { 357 compatible = "allwinner,sun20i-d1-i2c", 358 "allwinner,sun8i-v536-i2c", 359 "allwinner,sun6i-a31-i2c"; 360 reg = <0x2502c00 0x400>; 361 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&ccu CLK_BUS_I2C3>; 363 resets = <&ccu RST_BUS_I2C3>; 364 dmas = <&dma 46>, <&dma 46>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 }; 370 371 can0: can@2504000 { 372 compatible = "allwinner,sun20i-d1-can"; 373 reg = <0x02504000 0x400>; 374 interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&ccu CLK_BUS_CAN0>; 376 resets = <&ccu RST_BUS_CAN0>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&can0_pins>; 379 status = "disabled"; 380 }; 381 382 can1: can@2504400 { 383 compatible = "allwinner,sun20i-d1-can"; 384 reg = <0x02504400 0x400>; 385 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&ccu CLK_BUS_CAN1>; 387 resets = <&ccu RST_BUS_CAN1>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&can1_pins>; 390 status = "disabled"; 391 }; 392 393 syscon: syscon@3000000 { 394 compatible = "allwinner,sun20i-d1-system-control"; 395 reg = <0x3000000 0x1000>; 396 ranges; 397 #address-cells = <1>; 398 #size-cells = <1>; 399 }; 400 401 dma: dma-controller@3002000 { 402 compatible = "allwinner,sun20i-d1-dma"; 403 reg = <0x3002000 0x1000>; 404 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 406 clock-names = "bus", "mbus"; 407 resets = <&ccu RST_BUS_DMA>; 408 dma-channels = <16>; 409 dma-requests = <48>; 410 #dma-cells = <1>; 411 }; 412 413 sid: efuse@3006000 { 414 compatible = "allwinner,sun20i-d1-sid"; 415 reg = <0x3006000 0x1000>; 416 #address-cells = <1>; 417 #size-cells = <1>; 418 }; 419 420 crypto: crypto@3040000 { 421 compatible = "allwinner,sun20i-d1-crypto"; 422 reg = <0x3040000 0x800>; 423 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&ccu CLK_BUS_CE>, 425 <&ccu CLK_CE>, 426 <&ccu CLK_MBUS_CE>, 427 <&rtc CLK_IOSC>; 428 clock-names = "bus", "mod", "ram", "trng"; 429 resets = <&ccu RST_BUS_CE>; 430 }; 431 432 mbus: dram-controller@3102000 { 433 compatible = "allwinner,sun20i-d1-mbus"; 434 reg = <0x3102000 0x1000>, 435 <0x3103000 0x1000>; 436 reg-names = "mbus", "dram"; 437 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&ccu CLK_MBUS>, 439 <&ccu CLK_DRAM>, 440 <&ccu CLK_BUS_DRAM>; 441 clock-names = "mbus", "dram", "bus"; 442 dma-ranges = <0 0x40000000 0x80000000>; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 #interconnect-cells = <1>; 446 }; 447 448 mmc0: mmc@4020000 { 449 compatible = "allwinner,sun20i-d1-mmc"; 450 reg = <0x4020000 0x1000>; 451 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 453 clock-names = "ahb", "mmc"; 454 resets = <&ccu RST_BUS_MMC0>; 455 reset-names = "ahb"; 456 cap-sd-highspeed; 457 max-frequency = <150000000>; 458 no-mmc; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 }; 463 464 mmc1: mmc@4021000 { 465 compatible = "allwinner,sun20i-d1-mmc"; 466 reg = <0x4021000 0x1000>; 467 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 469 clock-names = "ahb", "mmc"; 470 resets = <&ccu RST_BUS_MMC1>; 471 reset-names = "ahb"; 472 cap-sd-highspeed; 473 max-frequency = <150000000>; 474 no-mmc; 475 status = "disabled"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 }; 479 480 mmc2: mmc@4022000 { 481 compatible = "allwinner,sun20i-d1-emmc", 482 "allwinner,sun50i-a100-emmc"; 483 reg = <0x4022000 0x1000>; 484 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 486 clock-names = "ahb", "mmc"; 487 resets = <&ccu RST_BUS_MMC2>; 488 reset-names = "ahb"; 489 cap-mmc-highspeed; 490 max-frequency = <150000000>; 491 mmc-ddr-1_8v; 492 mmc-ddr-3_3v; 493 no-sd; 494 no-sdio; 495 status = "disabled"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 }; 499 500 spi0: spi@4025000 { 501 compatible = "allwinner,sun20i-d1-spi", 502 "allwinner,sun50i-r329-spi"; 503 reg = <0x04025000 0x1000>; 504 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 506 clock-names = "ahb", "mod"; 507 dmas = <&dma 22>, <&dma 22>; 508 dma-names = "rx", "tx"; 509 resets = <&ccu RST_BUS_SPI0>; 510 status = "disabled"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 }; 514 515 spi1: spi@4026000 { 516 compatible = "allwinner,sun20i-d1-spi-dbi", 517 "allwinner,sun50i-r329-spi-dbi", 518 "allwinner,sun50i-r329-spi"; 519 reg = <0x04026000 0x1000>; 520 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 522 clock-names = "ahb", "mod"; 523 dmas = <&dma 23>, <&dma 23>; 524 dma-names = "rx", "tx"; 525 resets = <&ccu RST_BUS_SPI1>; 526 status = "disabled"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 }; 530 531 usb_otg: usb@4100000 { 532 compatible = "allwinner,sun20i-d1-musb", 533 "allwinner,sun8i-a33-musb"; 534 reg = <0x4100000 0x400>; 535 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "mc"; 537 clocks = <&ccu CLK_BUS_OTG>; 538 resets = <&ccu RST_BUS_OTG>; 539 extcon = <&usbphy 0>; 540 phys = <&usbphy 0>; 541 phy-names = "usb"; 542 status = "disabled"; 543 }; 544 545 usbphy: phy@4100400 { 546 compatible = "allwinner,sun20i-d1-usb-phy"; 547 reg = <0x4100400 0x100>, 548 <0x4101800 0x100>, 549 <0x4200800 0x100>; 550 reg-names = "phy_ctrl", 551 "pmu0", 552 "pmu1"; 553 clocks = <&dcxo>, 554 <&dcxo>; 555 clock-names = "usb0_phy", 556 "usb1_phy"; 557 resets = <&ccu RST_USB_PHY0>, 558 <&ccu RST_USB_PHY1>; 559 reset-names = "usb0_reset", 560 "usb1_reset"; 561 status = "disabled"; 562 #phy-cells = <1>; 563 }; 564 565 ehci0: usb@4101000 { 566 compatible = "allwinner,sun20i-d1-ehci", 567 "generic-ehci"; 568 reg = <0x4101000 0x100>; 569 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&ccu CLK_BUS_OHCI0>, 571 <&ccu CLK_BUS_EHCI0>, 572 <&ccu CLK_USB_OHCI0>; 573 resets = <&ccu RST_BUS_OHCI0>, 574 <&ccu RST_BUS_EHCI0>; 575 phys = <&usbphy 0>; 576 phy-names = "usb"; 577 status = "disabled"; 578 }; 579 580 ohci0: usb@4101400 { 581 compatible = "allwinner,sun20i-d1-ohci", 582 "generic-ohci"; 583 reg = <0x4101400 0x100>; 584 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&ccu CLK_BUS_OHCI0>, 586 <&ccu CLK_USB_OHCI0>; 587 resets = <&ccu RST_BUS_OHCI0>; 588 phys = <&usbphy 0>; 589 phy-names = "usb"; 590 status = "disabled"; 591 }; 592 593 ehci1: usb@4200000 { 594 compatible = "allwinner,sun20i-d1-ehci", 595 "generic-ehci"; 596 reg = <0x4200000 0x100>; 597 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&ccu CLK_BUS_OHCI1>, 599 <&ccu CLK_BUS_EHCI1>, 600 <&ccu CLK_USB_OHCI1>; 601 resets = <&ccu RST_BUS_OHCI1>, 602 <&ccu RST_BUS_EHCI1>; 603 phys = <&usbphy 1>; 604 phy-names = "usb"; 605 status = "disabled"; 606 }; 607 608 ohci1: usb@4200400 { 609 compatible = "allwinner,sun20i-d1-ohci", 610 "generic-ohci"; 611 reg = <0x4200400 0x100>; 612 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&ccu CLK_BUS_OHCI1>, 614 <&ccu CLK_USB_OHCI1>; 615 resets = <&ccu RST_BUS_OHCI1>; 616 phys = <&usbphy 1>; 617 phy-names = "usb"; 618 status = "disabled"; 619 }; 620 621 emac: ethernet@4500000 { 622 compatible = "allwinner,sun20i-d1-emac", 623 "allwinner,sun50i-a64-emac"; 624 reg = <0x4500000 0x10000>; 625 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "macirq"; 627 clocks = <&ccu CLK_BUS_EMAC>; 628 clock-names = "stmmaceth"; 629 resets = <&ccu RST_BUS_EMAC>; 630 reset-names = "stmmaceth"; 631 syscon = <&syscon>; 632 status = "disabled"; 633 634 mdio: mdio { 635 compatible = "snps,dwmac-mdio"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 }; 639 }; 640 641 display_clocks: clock-controller@5000000 { 642 compatible = "allwinner,sun20i-d1-de2-clk", 643 "allwinner,sun50i-h5-de2-clk"; 644 reg = <0x5000000 0x10000>; 645 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 646 clock-names = "bus", "mod"; 647 resets = <&ccu RST_BUS_DE>; 648 #clock-cells = <1>; 649 #reset-cells = <1>; 650 }; 651 652 mixer0: mixer@5100000 { 653 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 654 reg = <0x5100000 0x100000>; 655 clocks = <&display_clocks CLK_BUS_MIXER0>, 656 <&display_clocks CLK_MIXER0>; 657 clock-names = "bus", "mod"; 658 resets = <&display_clocks RST_MIXER0>; 659 660 ports { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 664 mixer0_out: port@1 { 665 reg = <1>; 666 667 mixer0_out_tcon_top_mixer0: endpoint { 668 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 669 }; 670 }; 671 }; 672 }; 673 674 mixer1: mixer@5200000 { 675 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 676 reg = <0x5200000 0x100000>; 677 clocks = <&display_clocks CLK_BUS_MIXER1>, 678 <&display_clocks CLK_MIXER1>; 679 clock-names = "bus", "mod"; 680 resets = <&display_clocks RST_MIXER1>; 681 682 ports { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 686 mixer1_out: port@1 { 687 reg = <1>; 688 689 mixer1_out_tcon_top_mixer1: endpoint { 690 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 691 }; 692 }; 693 }; 694 }; 695 696 dsi: dsi@5450000 { 697 compatible = "allwinner,sun20i-d1-mipi-dsi", 698 "allwinner,sun50i-a100-mipi-dsi"; 699 reg = <0x5450000 0x1000>; 700 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&ccu CLK_BUS_MIPI_DSI>, 702 <&tcon_top CLK_TCON_TOP_DSI>; 703 clock-names = "bus", "mod"; 704 resets = <&ccu RST_BUS_MIPI_DSI>; 705 phys = <&dphy>; 706 phy-names = "dphy"; 707 status = "disabled"; 708 709 port { 710 dsi_in_tcon_lcd0: endpoint { 711 remote-endpoint = <&tcon_lcd0_out_dsi>; 712 }; 713 }; 714 }; 715 716 dphy: phy@5451000 { 717 compatible = "allwinner,sun20i-d1-mipi-dphy", 718 "allwinner,sun50i-a100-mipi-dphy"; 719 reg = <0x5451000 0x1000>; 720 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&ccu CLK_BUS_MIPI_DSI>, 722 <&ccu CLK_MIPI_DSI>; 723 clock-names = "bus", "mod"; 724 resets = <&ccu RST_BUS_MIPI_DSI>; 725 #phy-cells = <0>; 726 }; 727 728 tcon_top: tcon-top@5460000 { 729 compatible = "allwinner,sun20i-d1-tcon-top"; 730 reg = <0x5460000 0x1000>; 731 clocks = <&ccu CLK_BUS_DPSS_TOP>, 732 <&ccu CLK_TCON_TV>, 733 <&ccu CLK_TVE>, 734 <&ccu CLK_TCON_LCD0>; 735 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 736 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 737 resets = <&ccu RST_BUS_DPSS_TOP>; 738 #clock-cells = <1>; 739 740 ports { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 744 tcon_top_mixer0_in: port@0 { 745 reg = <0>; 746 747 tcon_top_mixer0_in_mixer0: endpoint { 748 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 749 }; 750 }; 751 752 tcon_top_mixer0_out: port@1 { 753 reg = <1>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 758 reg = <0>; 759 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 760 }; 761 762 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 763 reg = <2>; 764 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 765 }; 766 }; 767 768 tcon_top_mixer1_in: port@2 { 769 reg = <2>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 773 tcon_top_mixer1_in_mixer1: endpoint@1 { 774 reg = <1>; 775 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 776 }; 777 }; 778 779 tcon_top_mixer1_out: port@3 { 780 reg = <3>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 784 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 785 reg = <0>; 786 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 787 }; 788 789 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 790 reg = <2>; 791 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 792 }; 793 }; 794 795 tcon_top_hdmi_in: port@4 { 796 reg = <4>; 797 798 tcon_top_hdmi_in_tcon_tv0: endpoint { 799 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 800 }; 801 }; 802 803 tcon_top_hdmi_out: port@5 { 804 reg = <5>; 805 }; 806 }; 807 }; 808 809 tcon_lcd0: lcd-controller@5461000 { 810 compatible = "allwinner,sun20i-d1-tcon-lcd"; 811 reg = <0x5461000 0x1000>; 812 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&ccu CLK_BUS_TCON_LCD0>, 814 <&ccu CLK_TCON_LCD0>; 815 clock-names = "ahb", "tcon-ch0"; 816 clock-output-names = "tcon-pixel-clock"; 817 resets = <&ccu RST_BUS_TCON_LCD0>, 818 <&ccu RST_BUS_LVDS0>; 819 reset-names = "lcd", "lvds"; 820 #clock-cells = <0>; 821 822 ports { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 826 tcon_lcd0_in: port@0 { 827 reg = <0>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 832 reg = <0>; 833 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 834 }; 835 836 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 837 reg = <1>; 838 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 839 }; 840 }; 841 842 tcon_lcd0_out: port@1 { 843 reg = <1>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 tcon_lcd0_out_dsi: endpoint@1 { 848 reg = <1>; 849 remote-endpoint = <&dsi_in_tcon_lcd0>; 850 }; 851 }; 852 }; 853 }; 854 855 tcon_tv0: lcd-controller@5470000 { 856 compatible = "allwinner,sun20i-d1-tcon-tv"; 857 reg = <0x5470000 0x1000>; 858 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&ccu CLK_BUS_TCON_TV>, 860 <&tcon_top CLK_TCON_TOP_TV0>; 861 clock-names = "ahb", "tcon-ch1"; 862 resets = <&ccu RST_BUS_TCON_TV>; 863 reset-names = "lcd"; 864 865 ports { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 tcon_tv0_in: port@0 { 870 reg = <0>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 874 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 875 reg = <0>; 876 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 877 }; 878 879 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 880 reg = <1>; 881 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 882 }; 883 }; 884 885 tcon_tv0_out: port@1 { 886 reg = <1>; 887 888 tcon_tv0_out_tcon_top_hdmi: endpoint { 889 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 890 }; 891 }; 892 }; 893 }; 894 895 ppu: power-controller@7001000 { 896 compatible = "allwinner,sun20i-d1-ppu"; 897 reg = <0x7001000 0x1000>; 898 clocks = <&r_ccu CLK_BUS_R_PPU>; 899 resets = <&r_ccu RST_BUS_R_PPU>; 900 #power-domain-cells = <1>; 901 }; 902 903 r_ccu: clock-controller@7010000 { 904 compatible = "allwinner,sun20i-d1-r-ccu"; 905 reg = <0x7010000 0x400>; 906 clocks = <&dcxo>, 907 <&rtc CLK_OSC32K>, 908 <&rtc CLK_IOSC>, 909 <&ccu CLK_PLL_PERIPH0_DIV3>; 910 clock-names = "hosc", "losc", "iosc", "pll-periph"; 911 #clock-cells = <1>; 912 #reset-cells = <1>; 913 }; 914 915 rtc: rtc@7090000 { 916 compatible = "allwinner,sun20i-d1-rtc", 917 "allwinner,sun50i-r329-rtc"; 918 reg = <0x7090000 0x400>; 919 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&r_ccu CLK_BUS_R_RTC>, 921 <&dcxo>, 922 <&r_ccu CLK_R_AHB>; 923 clock-names = "bus", "hosc", "ahb"; 924 #clock-cells = <1>; 925 }; 926 }; 927}; 928