1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* SPU ELF support for BFD.
3
4   Copyright 2006 Free Software Foundation, Inc.
5
6   This file is part of GDB, GAS, and the GNU binutils.
7
8 */
9
10
11/* These two enums are from rel_apu/common/spu_asm_format.h */
12/* definition of instruction format */
13typedef enum {
14  RRR,
15  RI18,
16  RI16,
17  RI10,
18  RI8,
19  RI7,
20  RR,
21  LBT,
22  LBTI,
23  IDATA,
24  UNKNOWN_IFORMAT
25} spu_iformat;
26
27/* These values describe assembly instruction arguments.  They indicate
28 * how to encode, range checking and which relocation to use. */
29typedef enum {
30  A_T,  /* register at pos 0 */
31  A_A,  /* register at pos 7 */
32  A_B,  /* register at pos 14 */
33  A_C,  /* register at pos 21 */
34  A_S,  /* special purpose register at pos 7 */
35  A_H,  /* channel register at pos 7 */
36  A_P,  /* parenthesis, this has to separate regs from immediates */
37  A_S3,
38  A_S6,
39  A_S7N,
40  A_S7,
41  A_U7A,
42  A_U7B,
43  A_S10B,
44  A_S10,
45  A_S11,
46  A_S11I,
47  A_S14,
48  A_S16,
49  A_S18,
50  A_R18,
51  A_U3,
52  A_U5,
53  A_U6,
54  A_U7,
55  A_U14,
56  A_X16,
57  A_U18,
58  A_MAX
59} spu_aformat;
60
61enum spu_insns {
62#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
63	TAG,
64#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
65	TAG,
66#include "spu-insns.h"
67#undef APUOP
68#undef APUOPFB
69        M_SPU_MAX
70};
71
72struct spu_opcode
73{
74   spu_iformat insn_type;
75   unsigned int opcode;
76   char *mnemonic;
77   int arg[5];
78};
79
80#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
81#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
82
83#define DECODE_INSN_RT(insn) (insn & 0x7f)
84#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
85#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
86#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
87
88#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
89#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
90
91/* For branching, immediate loads, hbr and  lqa/stqa. */
92#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
93#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
94
95/* for stop */
96#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
97
98/* For ila */
99#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
100#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
101
102/* For rotate and shift and generate control mask */
103#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
104#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
105
106/* For float <-> int conversion */
107#define DECODE_INSN_I8(insn)  SIGNED_EXTRACT(insn,8,14)
108#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
109
110/* For hbr  */
111#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
112#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
113#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
114#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
115
116