1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Performance counter support for POWER8 processors.
4 *
5 * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
6 */
7
8/*
9 * Power8 event codes.
10 */
11EVENT(PM_CYC,					0x0001e)
12EVENT(PM_GCT_NOSLOT_CYC,			0x100f8)
13EVENT(PM_CMPLU_STALL,				0x4000a)
14EVENT(PM_INST_CMPL,				0x00002)
15EVENT(PM_BRU_FIN,				0x10068)
16EVENT(PM_BR_MPRED_CMPL,				0x400f6)
17
18/* All L1 D cache load references counted at finish, gated by reject */
19EVENT(PM_LD_REF_L1,				0x100ee)
20/* Load Missed L1 */
21EVENT(PM_LD_MISS_L1,				0x3e054)
22/* Store Missed L1 */
23EVENT(PM_ST_MISS_L1,				0x300f0)
24/* L1 cache data prefetches */
25EVENT(PM_L1_PREF,				0x0d8b8)
26/* Instruction fetches from L1 */
27EVENT(PM_INST_FROM_L1,				0x04080)
28/* Demand iCache Miss */
29EVENT(PM_L1_ICACHE_MISS,			0x200fd)
30/* Instruction Demand sectors wriittent into IL1 */
31EVENT(PM_L1_DEMAND_WRITE,			0x0408c)
32/* Instruction prefetch written into IL1 */
33EVENT(PM_IC_PREF_WRITE,				0x0408e)
34/* The data cache was reloaded from local core's L3 due to a demand load */
35EVENT(PM_DATA_FROM_L3,				0x4c042)
36/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
37EVENT(PM_DATA_FROM_L3MISS,			0x300fe)
38/* All successful D-side store dispatches for this thread */
39EVENT(PM_L2_ST,					0x17080)
40/* All successful D-side store dispatches for this thread that were L2 Miss */
41EVENT(PM_L2_ST_MISS,				0x17082)
42/* Total HW L3 prefetches(Load+store) */
43EVENT(PM_L3_PREF_ALL,				0x4e052)
44/* Data PTEG reload */
45EVENT(PM_DTLB_MISS,				0x300fc)
46/* ITLB Reloaded */
47EVENT(PM_ITLB_MISS,				0x400fc)
48/* Run_Instructions */
49EVENT(PM_RUN_INST_CMPL,				0x500fa)
50/* Alternate event code for PM_RUN_INST_CMPL */
51EVENT(PM_RUN_INST_CMPL_ALT,			0x400fa)
52/* Run_cycles */
53EVENT(PM_RUN_CYC,				0x600f4)
54/* Alternate event code for Run_cycles */
55EVENT(PM_RUN_CYC_ALT,				0x200f4)
56/* Marked store completed */
57EVENT(PM_MRK_ST_CMPL,				0x10134)
58/* Alternate event code for Marked store completed */
59EVENT(PM_MRK_ST_CMPL_ALT,			0x301e2)
60/* Marked two path branch */
61EVENT(PM_BR_MRK_2PATH,				0x10138)
62/* Alternate event code for PM_BR_MRK_2PATH */
63EVENT(PM_BR_MRK_2PATH_ALT,			0x40138)
64/* L3 castouts in Mepf state */
65EVENT(PM_L3_CO_MEPF,				0x18082)
66/* Alternate event code for PM_L3_CO_MEPF */
67EVENT(PM_L3_CO_MEPF_ALT,			0x3e05e)
68/* Data cache was reloaded from a location other than L2 due to a marked load */
69EVENT(PM_MRK_DATA_FROM_L2MISS,			0x1d14e)
70/* Alternate event code for PM_MRK_DATA_FROM_L2MISS */
71EVENT(PM_MRK_DATA_FROM_L2MISS_ALT,		0x401e8)
72/* Alternate event code for  PM_CMPLU_STALL */
73EVENT(PM_CMPLU_STALL_ALT,			0x1e054)
74/* Two path branch */
75EVENT(PM_BR_2PATH,				0x20036)
76/* Alternate event code for PM_BR_2PATH */
77EVENT(PM_BR_2PATH_ALT,				0x40036)
78/* # PPC Dispatched */
79EVENT(PM_INST_DISP,				0x200f2)
80/* Alternate event code for PM_INST_DISP */
81EVENT(PM_INST_DISP_ALT,				0x300f2)
82/* Marked filter Match */
83EVENT(PM_MRK_FILT_MATCH,			0x2013c)
84/* Alternate event code for PM_MRK_FILT_MATCH */
85EVENT(PM_MRK_FILT_MATCH_ALT,			0x3012e)
86/* Alternate event code for PM_LD_MISS_L1 */
87EVENT(PM_LD_MISS_L1_ALT,			0x400f0)
88/*
89 * Memory Access Event -- mem_access
90 * Primary PMU event used here is PM_MRK_INST_CMPL, along with
91 * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).
92 */
93EVENT(MEM_ACCESS,				0x10401e0)
94