1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * uninorth.h: definitions for using the "UniNorth" host bridge chip
4 *             from Apple. This chip is used on "Core99" machines
5 *	       This also includes U2 used on more recent MacRISC2/3
6 *             machines and U3 (G5)
7 *
8 */
9#ifdef __KERNEL__
10#ifndef __ASM_UNINORTH_H__
11#define __ASM_UNINORTH_H__
12
13/*
14 * Uni-N and U3 config space reg. definitions
15 *
16 * (Little endian)
17 */
18
19/* Address ranges selection. This one should work with Bandit too */
20/* Not U3 */
21#define UNI_N_ADDR_SELECT		0x48
22#define UNI_N_ADDR_COARSE_MASK		0xffff0000	/* 256Mb regions at *0000000 */
23#define UNI_N_ADDR_FINE_MASK		0x0000ffff	/*  16Mb regions at f*000000 */
24
25/* AGP registers */
26/* Not U3 */
27#define UNI_N_CFG_GART_BASE		0x8c
28#define UNI_N_CFG_AGP_BASE		0x90
29#define UNI_N_CFG_GART_CTRL		0x94
30#define UNI_N_CFG_INTERNAL_STATUS	0x98
31#define UNI_N_CFG_GART_DUMMY_PAGE	0xa4
32
33/* UNI_N_CFG_GART_CTRL bits definitions */
34#define UNI_N_CFG_GART_INVAL		0x00000001
35#define UNI_N_CFG_GART_ENABLE		0x00000100
36#define UNI_N_CFG_GART_2xRESET		0x00010000
37#define UNI_N_CFG_GART_DISSBADET	0x00020000
38/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
39#define U3_N_CFG_GART_SYNCMODE		0x00040000
40#define U3_N_CFG_GART_PERFRD		0x00080000
41#define U3_N_CFG_GART_B2BGNT		0x00200000
42#define U3_N_CFG_GART_FASTDDR		0x00400000
43
44/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
45 * revision 1.5 (x4 AGP) may need further changes.
46 *
47 * AGP_BASE register contains the base address of the AGP aperture on
48 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
49 * even if decoding of this address range is enabled in the address select
50 * register. Apparently, the only supported bases are 256Mb multiples
51 * (high 4 bits of that register).
52 *
53 * GART_BASE register appear to contain the physical address of the GART
54 * in system memory in the high address bits (page aligned), and the
55 * GART size in the low order bits (number of GART pages)
56 *
57 * The GART format itself is one 32bits word per physical memory page.
58 * This word contains, in little-endian format (!!!), the physical address
59 * of the page in the high bits, and what appears to be an "enable" bit
60 * in the LSB bit (0) that must be set to 1 when the entry is valid.
61 *
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
64 * cachable). AGP memory itself doesn't seem to be cache coherent neither.
65 *
66 * In order to invalidate the GART (which is probably necessary to inval
67 * the bridge internal TLBs), the following sequence has to be written,
68 * in order, to the GART_CTRL register:
69 *
70 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
71 *   UNI_N_CFG_GART_ENABLE
72 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
73 *   UNI_N_CFG_GART_ENABLE
74 *
75 * As far as AGP "features" are concerned, it looks like fast write may
76 * not be supported but this has to be confirmed.
77 *
78 * Turning on AGP seem to require a double invalidate operation, one before
79 * setting the AGP command register, on after.
80 *
81 * Turning off AGP seems to require the following sequence: first wait
82 * for the AGP to be idle by reading the internal status register, then
83 * write in that order to the GART_CTRL register:
84 *
85 *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
86 *   0
87 *   UNI_N_CFG_GART_2xRESET
88 *   0
89 */
90
91/*
92 * Uni-N memory mapped reg. definitions
93 *
94 * Those registers are Big-Endian !!
95 *
96 * Their meaning come from either Darwin and/or from experiments I made with
97 * the bootrom, I'm not sure about their exact meaning yet
98 *
99 */
100
101/* Version of the UniNorth chip */
102#define UNI_N_VERSION			0x0000		/* Known versions: 3,7 and 8 */
103
104#define UNI_N_VERSION_107		0x0003		/* 1.0.7 */
105#define UNI_N_VERSION_10A		0x0007		/* 1.0.10 */
106#define UNI_N_VERSION_150		0x0011		/* 1.5 */
107#define UNI_N_VERSION_200		0x0024		/* 2.0 */
108#define UNI_N_VERSION_PANGEA		0x00C0		/* Integrated U1 + K */
109#define UNI_N_VERSION_INTREPID		0x00D2		/* Integrated U2 + K */
110#define UNI_N_VERSION_300		0x0030		/* 3.0 (U3 on G5) */
111
112/* This register is used to enable/disable various clocks */
113#define UNI_N_CLOCK_CNTL		0x0020
114#define UNI_N_CLOCK_CNTL_PCI		0x00000001	/* PCI2 clock control */
115#define UNI_N_CLOCK_CNTL_GMAC		0x00000002	/* GMAC clock control */
116#define UNI_N_CLOCK_CNTL_FW		0x00000004	/* FireWire clock control */
117#define UNI_N_CLOCK_CNTL_ATA100		0x00000010	/* ATA-100 clock control (U2) */
118
119/* Power Management control */
120#define UNI_N_POWER_MGT			0x0030
121#define UNI_N_POWER_MGT_NORMAL		0x00
122#define UNI_N_POWER_MGT_IDLE2		0x01
123#define UNI_N_POWER_MGT_SLEEP		0x02
124
125/* This register is configured by Darwin depending on the UniN
126 * revision
127 */
128#define UNI_N_ARB_CTRL			0x0040
129#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT	15
130#define UNI_N_ARB_CTRL_QACK_DELAY_MASK	0x0e1f8000
131#define UNI_N_ARB_CTRL_QACK_DELAY	0x30
132#define UNI_N_ARB_CTRL_QACK_DELAY105	0x00
133
134/* This one _might_ return the CPU number of the CPU reading it;
135 * the bootROM decides whether to boot or to sleep/spinloop depending
136 * on this register being 0 or not
137 */
138#define UNI_N_CPU_NUMBER		0x0050
139
140/* This register appear to be read by the bootROM to decide what
141 *  to do on a non-recoverable reset (powerup or wakeup)
142 */
143#define UNI_N_HWINIT_STATE		0x0070
144#define UNI_N_HWINIT_STATE_SLEEPING	0x01
145#define UNI_N_HWINIT_STATE_RUNNING	0x02
146/* This last bit appear to be used by the bootROM to know the second
147 * CPU has started and will enter it's sleep loop with IP=0
148 */
149#define UNI_N_HWINIT_STATE_CPU1_FLAG	0x10000000
150
151/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
152 * is in low speed mode.
153 */
154#define UNI_N_AACK_DELAY		0x0100
155#define UNI_N_AACK_DELAY_ENABLE		0x00000001
156
157/* Clock status for Intrepid */
158#define UNI_N_CLOCK_STOP_STATUS0	0x0150
159#define UNI_N_CLOCK_STOPPED_EXTAGP	0x00200000
160#define UNI_N_CLOCK_STOPPED_AGPDEL	0x00100000
161#define UNI_N_CLOCK_STOPPED_I2S0_45_49	0x00080000
162#define UNI_N_CLOCK_STOPPED_I2S0_18	0x00040000
163#define UNI_N_CLOCK_STOPPED_I2S1_45_49	0x00020000
164#define UNI_N_CLOCK_STOPPED_I2S1_18	0x00010000
165#define UNI_N_CLOCK_STOPPED_TIMER	0x00008000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18	0x00004000
167#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32	0x00002000
168#define UNI_N_CLOCK_STOPPED_SCC_VIA32	0x00001000
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT0	0x00000800
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT1	0x00000400
171#define UNI_N_CLOCK_STOPPED_SCC_SLOT2	0x00000200
172#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO	0x00000100
173#define UNI_N_CLOCK_STOPPED_VEO0	0x00000080
174#define UNI_N_CLOCK_STOPPED_VEO1	0x00000040
175#define UNI_N_CLOCK_STOPPED_USB0	0x00000020
176#define UNI_N_CLOCK_STOPPED_USB1	0x00000010
177#define UNI_N_CLOCK_STOPPED_USB2	0x00000008
178#define UNI_N_CLOCK_STOPPED_32		0x00000004
179#define UNI_N_CLOCK_STOPPED_45		0x00000002
180#define UNI_N_CLOCK_STOPPED_49		0x00000001
181
182#define UNI_N_CLOCK_STOP_STATUS1	0x0160
183#define UNI_N_CLOCK_STOPPED_PLL4REF	0x00080000
184#define UNI_N_CLOCK_STOPPED_CPUDEL	0x00040000
185#define UNI_N_CLOCK_STOPPED_CPU		0x00020000
186#define UNI_N_CLOCK_STOPPED_BUF_REFCKO	0x00010000
187#define UNI_N_CLOCK_STOPPED_PCI2	0x00008000
188#define UNI_N_CLOCK_STOPPED_FW		0x00004000
189#define UNI_N_CLOCK_STOPPED_GB		0x00002000
190#define UNI_N_CLOCK_STOPPED_ATA66	0x00001000
191#define UNI_N_CLOCK_STOPPED_ATA100	0x00000800
192#define UNI_N_CLOCK_STOPPED_MAX		0x00000400
193#define UNI_N_CLOCK_STOPPED_PCI1	0x00000200
194#define UNI_N_CLOCK_STOPPED_KLPCI	0x00000100
195#define UNI_N_CLOCK_STOPPED_USB0PCI	0x00000080
196#define UNI_N_CLOCK_STOPPED_USB1PCI	0x00000040
197#define UNI_N_CLOCK_STOPPED_USB2PCI	0x00000020
198#define UNI_N_CLOCK_STOPPED_7PCI1	0x00000008
199#define UNI_N_CLOCK_STOPPED_AGP		0x00000004
200#define UNI_N_CLOCK_STOPPED_PCI0	0x00000002
201#define UNI_N_CLOCK_STOPPED_18		0x00000001
202
203/* Intrepid registe to OF do-platform-clockspreading */
204#define UNI_N_CLOCK_SPREADING		0x190
205
206/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
207
208
209/*
210 * U3 specific registers
211 */
212
213
214/* U3 Toggle */
215#define U3_TOGGLE_REG			0x00e0
216#define U3_PMC_START_STOP		0x0001
217#define U3_MPIC_RESET			0x0002
218#define U3_MPIC_OUTPUT_ENABLE		0x0004
219
220/* U3 API PHY Config 1 */
221#define U3_API_PHY_CONFIG_1		0x23030
222
223/* U3 HyperTransport registers */
224#define U3_HT_CONFIG_BASE      		0x70000
225#define U3_HT_LINK_COMMAND		0x100
226#define U3_HT_LINK_CONFIG		0x110
227#define U3_HT_LINK_FREQ			0x120
228
229#endif /* __ASM_UNINORTH_H__ */
230#endif /* __KERNEL__ */
231