1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Contains register definitions for the Freescale Embedded Performance
4 * Monitor.
5 */
6#ifdef __KERNEL__
7#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
8#define __ASM_POWERPC_REG_FSL_EMB_H__
9
10#include <linux/stringify.h>
11
12#ifndef __ASSEMBLY__
13/* Performance Monitor Registers */
14static __always_inline unsigned int mfpmr(unsigned int rn)
15{
16	unsigned int rval;
17
18	asm (".machine push; "
19	     ".machine e300; "
20	     "mfpmr %[rval], %[rn];"
21	     ".machine pop;"
22	     : [rval] "=r" (rval) : [rn] "i" (rn));
23
24	return rval;
25}
26
27static __always_inline void mtpmr(unsigned int rn, unsigned int val)
28{
29	asm (".machine push; "
30	     ".machine e300; "
31	     "mtpmr %[rn], %[val];"
32	     ".machine pop;"
33	     : [val] "=r" (val) : [rn] "i" (rn));
34}
35#endif /* __ASSEMBLY__ */
36
37/* Freescale Book E Performance Monitor APU Registers */
38#define PMRN_PMC0	0x010	/* Performance Monitor Counter 0 */
39#define PMRN_PMC1	0x011	/* Performance Monitor Counter 1 */
40#define PMRN_PMC2	0x012	/* Performance Monitor Counter 2 */
41#define PMRN_PMC3	0x013	/* Performance Monitor Counter 3 */
42#define PMRN_PMC4	0x014	/* Performance Monitor Counter 4 */
43#define PMRN_PMC5	0x015	/* Performance Monitor Counter 5 */
44#define PMRN_PMLCA0	0x090	/* PM Local Control A0 */
45#define PMRN_PMLCA1	0x091	/* PM Local Control A1 */
46#define PMRN_PMLCA2	0x092	/* PM Local Control A2 */
47#define PMRN_PMLCA3	0x093	/* PM Local Control A3 */
48#define PMRN_PMLCA4	0x094	/* PM Local Control A4 */
49#define PMRN_PMLCA5	0x095	/* PM Local Control A5 */
50
51#define PMLCA_FC	0x80000000	/* Freeze Counter */
52#define PMLCA_FCS	0x40000000	/* Freeze in Supervisor */
53#define PMLCA_FCU	0x20000000	/* Freeze in User */
54#define PMLCA_FCM1	0x10000000	/* Freeze when PMM==1 */
55#define PMLCA_FCM0	0x08000000	/* Freeze when PMM==0 */
56#define PMLCA_CE	0x04000000	/* Condition Enable */
57#define PMLCA_FGCS1	0x00000002	/* Freeze in guest state */
58#define PMLCA_FGCS0	0x00000001	/* Freeze in hypervisor state */
59
60#define PMLCA_EVENT_MASK 0x01ff0000	/* Event field */
61#define PMLCA_EVENT_SHIFT	16
62
63#define PMRN_PMLCB0	0x110	/* PM Local Control B0 */
64#define PMRN_PMLCB1	0x111	/* PM Local Control B1 */
65#define PMRN_PMLCB2	0x112	/* PM Local Control B2 */
66#define PMRN_PMLCB3	0x113	/* PM Local Control B3 */
67#define PMRN_PMLCB4	0x114	/* PM Local Control B4 */
68#define PMRN_PMLCB5	0x115	/* PM Local Control B5 */
69
70#define PMLCB_THRESHMUL_MASK	0x0700	/* Threshold Multiple Field */
71#define PMLCB_THRESHMUL_SHIFT	8
72
73#define PMLCB_THRESHOLD_MASK	0x003f	/* Threshold Field */
74#define PMLCB_THRESHOLD_SHIFT	0
75
76#define PMRN_PMGC0	0x190	/* PM Global Control 0 */
77
78#define PMGC0_FAC	0x80000000	/* Freeze all Counters */
79#define PMGC0_PMIE	0x40000000	/* Interrupt Enable */
80#define PMGC0_FCECE	0x20000000	/* Freeze countes on
81					   Enabled Condition or
82					   Event */
83
84#define PMRN_UPMC0	0x000	/* User Performance Monitor Counter 0 */
85#define PMRN_UPMC1	0x001	/* User Performance Monitor Counter 1 */
86#define PMRN_UPMC2	0x002	/* User Performance Monitor Counter 2 */
87#define PMRN_UPMC3	0x003	/* User Performance Monitor Counter 3 */
88#define PMRN_UPMC4	0x004	/* User Performance Monitor Counter 4 */
89#define PMRN_UPMC5	0x005	/* User Performance Monitor Counter 5 */
90#define PMRN_UPMLCA0	0x080	/* User PM Local Control A0 */
91#define PMRN_UPMLCA1	0x081	/* User PM Local Control A1 */
92#define PMRN_UPMLCA2	0x082	/* User PM Local Control A2 */
93#define PMRN_UPMLCA3	0x083	/* User PM Local Control A3 */
94#define PMRN_UPMLCA4	0x084	/* User PM Local Control A4 */
95#define PMRN_UPMLCA5	0x085	/* User PM Local Control A5 */
96#define PMRN_UPMLCB0	0x100	/* User PM Local Control B0 */
97#define PMRN_UPMLCB1	0x101	/* User PM Local Control B1 */
98#define PMRN_UPMLCB2	0x102	/* User PM Local Control B2 */
99#define PMRN_UPMLCB3	0x103	/* User PM Local Control B3 */
100#define PMRN_UPMLCB4	0x104	/* User PM Local Control B4 */
101#define PMRN_UPMLCB5	0x105	/* User PM Local Control B5 */
102#define PMRN_UPMGC0	0x180	/* User PM Global Control 0 */
103
104
105#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
106#endif /* __KERNEL__ */
107