1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2#ifndef _ASM_POWERPC_PCI_BRIDGE_H 3#define _ASM_POWERPC_PCI_BRIDGE_H 4#ifdef __KERNEL__ 5/* 6 */ 7#include <linux/pci.h> 8#include <linux/list.h> 9#include <linux/ioport.h> 10#include <linux/numa.h> 11#include <linux/iommu.h> 12 13struct device_node; 14 15/* 16 * PCI controller operations 17 */ 18struct pci_controller_ops { 19 void (*dma_dev_setup)(struct pci_dev *pdev); 20 void (*dma_bus_setup)(struct pci_bus *bus); 21 bool (*iommu_bypass_supported)(struct pci_dev *pdev, 22 u64 mask); 23 24 int (*probe_mode)(struct pci_bus *bus); 25 26 /* Called when pci_enable_device() is called. Returns true to 27 * allow assignment/enabling of the device. */ 28 bool (*enable_device_hook)(struct pci_dev *pdev); 29 30 void (*disable_device)(struct pci_dev *pdev); 31 32 void (*release_device)(struct pci_dev *pdev); 33 34 /* Called during PCI resource reassignment */ 35 resource_size_t (*window_alignment)(struct pci_bus *bus, 36 unsigned long type); 37 void (*setup_bridge)(struct pci_bus *bus, 38 unsigned long type); 39 void (*reset_secondary_bus)(struct pci_dev *pdev); 40 41#ifdef CONFIG_PCI_MSI 42 int (*setup_msi_irqs)(struct pci_dev *pdev, 43 int nvec, int type); 44 void (*teardown_msi_irqs)(struct pci_dev *pdev); 45#endif 46 47 void (*shutdown)(struct pci_controller *hose); 48 49 struct iommu_group *(*device_group)(struct pci_controller *hose, 50 struct pci_dev *pdev); 51}; 52 53/* 54 * Structure of a PCI controller (host bridge) 55 */ 56struct pci_controller { 57 struct pci_bus *bus; 58 char is_dynamic; 59#ifdef CONFIG_PPC64 60 int node; 61#endif 62 struct device_node *dn; 63 struct list_head list_node; 64 struct device *parent; 65 66 int first_busno; 67 int last_busno; 68 int self_busno; 69 struct resource busn; 70 71 void __iomem *io_base_virt; 72#ifdef CONFIG_PPC64 73 void __iomem *io_base_alloc; 74#endif 75 resource_size_t io_base_phys; 76 resource_size_t pci_io_size; 77 78 /* Some machines have a special region to forward the ISA 79 * "memory" cycles such as VGA memory regions. Left to 0 80 * if unsupported 81 */ 82 resource_size_t isa_mem_phys; 83 resource_size_t isa_mem_size; 84 85 struct pci_controller_ops controller_ops; 86 struct pci_ops *ops; 87 unsigned int __iomem *cfg_addr; 88 void __iomem *cfg_data; 89 90 /* 91 * Used for variants of PCI indirect handling and possible quirks: 92 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 93 * EXT_REG - provides access to PCI-e extended registers 94 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 95 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 96 * to determine which bus number to match on when generating type0 97 * config cycles 98 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 99 * hanging if we don't have link and try to do config cycles to 100 * anything but the PHB. Only allow talking to the PHB if this is 101 * set. 102 * BIG_ENDIAN - cfg_addr is a big endian register 103 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 104 * the PLB4. Effectively disable MRM commands by setting this. 105 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe 106 * link status is in a RC PCIe cfg register (vs being a SoC register) 107 */ 108#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 109#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 110#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 111#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 112#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 113#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 114#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 115 u32 indirect_type; 116 /* Currently, we limit ourselves to 1 IO range and 3 mem 117 * ranges since the common pci_bus structure can't handle more 118 */ 119 struct resource io_resource; 120 struct resource mem_resources[3]; 121 resource_size_t mem_offset[3]; 122 int global_number; /* PCI domain number */ 123 124 resource_size_t dma_window_base_cur; 125 resource_size_t dma_window_size; 126 127#ifdef CONFIG_PPC64 128 unsigned long buid; 129 struct pci_dn *pci_data; 130#endif /* CONFIG_PPC64 */ 131 132 void *private_data; 133 134 /* IRQ domain hierarchy */ 135 struct irq_domain *dev_domain; 136 struct irq_domain *msi_domain; 137 struct fwnode_handle *fwnode; 138 139 /* iommu_ops support */ 140 struct iommu_device iommu; 141}; 142 143/* These are used for config access before all the PCI probing 144 has been done. */ 145extern int early_read_config_byte(struct pci_controller *hose, int bus, 146 int dev_fn, int where, u8 *val); 147extern int early_read_config_word(struct pci_controller *hose, int bus, 148 int dev_fn, int where, u16 *val); 149extern int early_read_config_dword(struct pci_controller *hose, int bus, 150 int dev_fn, int where, u32 *val); 151extern int early_write_config_byte(struct pci_controller *hose, int bus, 152 int dev_fn, int where, u8 val); 153extern int early_write_config_word(struct pci_controller *hose, int bus, 154 int dev_fn, int where, u16 val); 155extern int early_write_config_dword(struct pci_controller *hose, int bus, 156 int dev_fn, int where, u32 val); 157 158extern int early_find_capability(struct pci_controller *hose, int bus, 159 int dev_fn, int cap); 160 161extern void setup_indirect_pci(struct pci_controller* hose, 162 resource_size_t cfg_addr, 163 resource_size_t cfg_data, u32 flags); 164 165extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, 166 int offset, int len, u32 *val); 167 168extern int __indirect_read_config(struct pci_controller *hose, 169 unsigned char bus_number, unsigned int devfn, 170 int offset, int len, u32 *val); 171 172extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, 173 int offset, int len, u32 val); 174 175static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 176{ 177 return bus->sysdata; 178} 179 180#ifdef CONFIG_PPC_PMAC 181extern int pci_device_from_OF_node(struct device_node *node, 182 u8 *bus, u8 *devfn); 183#endif 184#ifndef CONFIG_PPC64 185 186#ifdef CONFIG_PPC_PCI_OF_BUS_MAP 187extern void pci_create_OF_bus_map(void); 188#else 189static inline void pci_create_OF_bus_map(void) {} 190#endif 191 192#else /* CONFIG_PPC64 */ 193 194/* 195 * PCI stuff, for nodes representing PCI devices, pointed to 196 * by device_node->data. 197 */ 198struct iommu_table; 199 200struct pci_dn { 201 int flags; 202#define PCI_DN_FLAG_IOV_VF 0x01 203#define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */ 204 205 int busno; /* pci bus number */ 206 int devfn; /* pci device and function number */ 207 int vendor_id; /* Vendor ID */ 208 int device_id; /* Device ID */ 209 int class_code; /* Device class code */ 210 211 struct pci_dn *parent; 212 struct pci_controller *phb; /* for pci devices */ 213 struct iommu_table_group *table_group; /* for phb's or bridges */ 214 215 int pci_ext_config_space; /* for pci devices */ 216#ifdef CONFIG_EEH 217 struct eeh_dev *edev; /* eeh device */ 218#endif 219#define IODA_INVALID_PE 0xFFFFFFFF 220 unsigned int pe_number; 221#ifdef CONFIG_PCI_IOV 222 u16 vfs_expanded; /* number of VFs IOV BAR expanded */ 223 u16 num_vfs; /* number of VFs enabled*/ 224 unsigned int *pe_num_map; /* PE# for the first VF PE or array */ 225 bool m64_single_mode; /* Use M64 BAR in Single Mode */ 226#define IODA_INVALID_M64 (-1) 227 int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */ 228 int last_allow_rc; /* Only used on pseries */ 229#endif /* CONFIG_PCI_IOV */ 230 int mps; /* Maximum Payload Size */ 231 struct list_head child_list; 232 struct list_head list; 233 struct resource holes[PCI_SRIOV_NUM_BARS]; 234}; 235 236/* Get the pointer to a device_node's pci_dn */ 237#define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 238 239extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, 240 int devfn); 241extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); 242extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose, 243 struct device_node *dn); 244extern void pci_remove_device_node_info(struct device_node *dn); 245 246#ifdef CONFIG_PCI_IOV 247struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev); 248void remove_sriov_vf_pdns(struct pci_dev *pdev); 249#endif 250 251#if defined(CONFIG_EEH) 252static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) 253{ 254 return pdn ? pdn->edev : NULL; 255} 256#else 257#define pdn_to_eeh_dev(x) (NULL) 258#endif 259 260/** Find the bus corresponding to the indicated device node */ 261extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn); 262 263/** Remove all of the PCI devices under this bus */ 264extern void pci_hp_remove_devices(struct pci_bus *bus); 265 266/** Discover new pci devices under this bus, and add them */ 267extern void pci_hp_add_devices(struct pci_bus *bus); 268 269extern int pcibios_unmap_io_space(struct pci_bus *bus); 270extern int pcibios_map_io_space(struct pci_bus *bus); 271 272#ifdef CONFIG_NUMA 273#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 274#else 275#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE) 276#endif 277 278#endif /* CONFIG_PPC64 */ 279 280/* Get the PCI host controller for an OF device */ 281extern struct pci_controller *pci_find_hose_for_OF_device( 282 struct device_node* node); 283 284extern struct pci_controller *pci_find_controller_for_domain(int domain_nr); 285 286/* Fill up host controller resources from the OF node */ 287extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 288 struct device_node *dev, int primary); 289 290/* Allocate & free a PCI host bridge structure */ 291extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 292extern void pcibios_free_controller(struct pci_controller *phb); 293extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge); 294 295#ifdef CONFIG_PCI 296extern int pcibios_vaddr_is_ioport(void __iomem *address); 297#else 298static inline int pcibios_vaddr_is_ioport(void __iomem *address) 299{ 300 return 0; 301} 302#endif /* CONFIG_PCI */ 303 304#endif /* __KERNEL__ */ 305#endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 306