1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2006-2008 PA Semi, Inc 4 * 5 * Hardware register layout and descriptor formats for the on-board 6 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security 7 * drivers. 8 */ 9 10#ifndef ASM_PASEMI_DMA_H 11#define ASM_PASEMI_DMA_H 12 13/* status register layout in IOB region, at 0xfb800000 */ 14struct pasdma_status { 15 u64 rx_sta[64]; /* RX channel status */ 16 u64 tx_sta[20]; /* TX channel status */ 17}; 18 19 20/* All these registers live in the PCI configuration space for the DMA PCI 21 * device. Use the normal PCI config access functions for them. 22 */ 23enum { 24 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */ 25 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */ 26 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */ 27 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ 28 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ 29 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ 30 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ 31 PAS_DMA_COM_CFG = 0x114, /* Common config reg */ 32 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */ 33 PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */ 34 PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */ 35 PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */ 36}; 37 38 39#define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */ 40#define PAS_DMA_CAP_TXCH_TCHN_S 16 41 42#define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */ 43#define PAS_DMA_CAP_RXCH_RCHN_S 16 44 45#define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */ 46#define PAS_DMA_CAP_IFI_IOFF_S 24 47#define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */ 48#define PAS_DMA_CAP_IFI_NIN_S 16 49 50#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ 51#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ 52#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ 53#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ 54 55 56/* Per-interface and per-channel registers */ 57#define _PAS_DMA_RXINT_STRIDE 0x20 58#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE) 59#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001 60#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002 61#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008 62#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010 63#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020 64#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040 65#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800 66#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000 67#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000 68#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000 69#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000 70#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000 71#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000 72#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17 73#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE) 74#define PAS_DMA_RXINT_CFG_RBP 0x80000000 75#define PAS_DMA_RXINT_CFG_ITRR 0x40000000 76#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000 77#define PAS_DMA_RXINT_CFG_DHL_S 24 78#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \ 79 PAS_DMA_RXINT_CFG_DHL_M) 80#define PAS_DMA_RXINT_CFG_ITR 0x00400000 81#define PAS_DMA_RXINT_CFG_LW 0x00200000 82#define PAS_DMA_RXINT_CFG_L2 0x00100000 83#define PAS_DMA_RXINT_CFG_HEN 0x00080000 84#define PAS_DMA_RXINT_CFG_WIF 0x00000002 85#define PAS_DMA_RXINT_CFG_WIL 0x00000001 86 87#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE) 88#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff 89#define PAS_DMA_RXINT_INCR_INCR_S 0 90#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff) 91#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE) 92#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f) 93#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE) 94#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff) 95#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */ 96#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */ 97#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \ 98 PAS_DMA_RXINT_BASEU_SIZ_M) 99 100 101#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ 102#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ 103#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ 104#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ 105#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ 106#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ 107#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ 108#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ 109#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) 110#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ 111#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ 112#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ 113#define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800 114#define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400 115#define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200 116#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100 117#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) 118#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ 119#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */ 120#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */ 121#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */ 122#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c 123#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 124#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ 125 PAS_DMA_TXCHAN_CFG_TATTR_M) 126#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800 127#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400 128#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0 129#define PAS_DMA_TXCHAN_CFG_WT_S 6 130#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ 131 PAS_DMA_TXCHAN_CFG_WT_M) 132#define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */ 133#define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */ 134#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ 135#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ 136#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ 137#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) 138#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) 139#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 140#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 141#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ 142 PAS_DMA_TXCHAN_BASEL_BRBL_M) 143#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) 144#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff 145#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 146#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ 147 PAS_DMA_TXCHAN_BASEU_BRBH_M) 148/* # of cache lines worth of buffer ring */ 149#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 150#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ 151#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ 152 PAS_DMA_TXCHAN_BASEU_SIZ_M) 153 154#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */ 155#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */ 156#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */ 157#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */ 158#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */ 159#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */ 160#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */ 161#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE) 162#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */ 163#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */ 164#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */ 165#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000 166#define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000 167#define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000 168#define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800 169#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE) 170#define PAS_DMA_RXCHAN_CFG_CTR 0x00000400 171#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380 172#define PAS_DMA_RXCHAN_CFG_HBU_S 7 173#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \ 174 PAS_DMA_RXCHAN_CFG_HBU_M) 175#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE) 176#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE) 177#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0 178#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0 179#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \ 180 PAS_DMA_RXCHAN_BASEL_BRBL_M) 181#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE) 182#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff 183#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0 184#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \ 185 PAS_DMA_RXCHAN_BASEU_BRBH_M) 186/* # of cache lines worth of buffer ring */ 187#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000 188#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ 189#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \ 190 PAS_DMA_RXCHAN_BASEU_SIZ_M) 191 192#define PAS_STATUS_PCNT_M 0x000000000000ffffull 193#define PAS_STATUS_PCNT_S 0 194#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull 195#define PAS_STATUS_DCNT_S 16 196#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull 197#define PAS_STATUS_BPCNT_S 32 198#define PAS_STATUS_CAUSE_M 0xf000000000000000ull 199#define PAS_STATUS_TIMER 0x1000000000000000ull 200#define PAS_STATUS_ERROR 0x2000000000000000ull 201#define PAS_STATUS_SOFT 0x4000000000000000ull 202#define PAS_STATUS_INT 0x8000000000000000ull 203 204#define PAS_IOB_COM_PKTHDRCNT 0x120 205#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000 206#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16 207#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff 208#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0 209 210#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) 211#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff 212#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 213#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ 214 PAS_IOB_DMA_RXCH_CFG_CNTTH_M) 215#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) 216#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff 217#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 218#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ 219 PAS_IOB_DMA_TXCH_CFG_CNTTH_M) 220#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) 221#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 222#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff 223#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 224#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ 225 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) 226#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) 227#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 228#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff 229#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 230#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ 231 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) 232#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) 233#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 234#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 235#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ 236 PAS_IOB_DMA_RXCH_RESET_PCNT_M) 237#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 238#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 239#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 240#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 241#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 242#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 243#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) 244#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 245#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 246#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ 247 PAS_IOB_DMA_TXCH_RESET_PCNT_M) 248#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 249#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 250#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 251#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 252#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 253#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 254 255#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 256#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff 257#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 258#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ 259 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) 260 261/* Transmit descriptor fields */ 262#define XCT_MACTX_T 0x8000000000000000ull 263#define XCT_MACTX_ST 0x4000000000000000ull 264#define XCT_MACTX_NORES 0x0000000000000000ull 265#define XCT_MACTX_8BRES 0x1000000000000000ull 266#define XCT_MACTX_24BRES 0x2000000000000000ull 267#define XCT_MACTX_40BRES 0x3000000000000000ull 268#define XCT_MACTX_I 0x0800000000000000ull 269#define XCT_MACTX_O 0x0400000000000000ull 270#define XCT_MACTX_E 0x0200000000000000ull 271#define XCT_MACTX_VLAN_M 0x0180000000000000ull 272#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull 273#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull 274#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull 275#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull 276#define XCT_MACTX_CRC_M 0x0060000000000000ull 277#define XCT_MACTX_CRC_NOP 0x0000000000000000ull 278#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull 279#define XCT_MACTX_CRC_PAD 0x0040000000000000ull 280#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull 281#define XCT_MACTX_SS 0x0010000000000000ull 282#define XCT_MACTX_LLEN_M 0x00007fff00000000ull 283#define XCT_MACTX_LLEN_S 32ull 284#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ 285 XCT_MACTX_LLEN_M) 286#define XCT_MACTX_IPH_M 0x00000000f8000000ull 287#define XCT_MACTX_IPH_S 27ull 288#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ 289 XCT_MACTX_IPH_M) 290#define XCT_MACTX_IPO_M 0x0000000007c00000ull 291#define XCT_MACTX_IPO_S 22ull 292#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ 293 XCT_MACTX_IPO_M) 294#define XCT_MACTX_CSUM_M 0x0000000000000060ull 295#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull 296#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull 297#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull 298#define XCT_MACTX_V6 0x0000000000000010ull 299#define XCT_MACTX_C 0x0000000000000004ull 300#define XCT_MACTX_AL2 0x0000000000000002ull 301 302/* Receive descriptor fields */ 303#define XCT_MACRX_T 0x8000000000000000ull 304#define XCT_MACRX_ST 0x4000000000000000ull 305#define XCT_MACRX_RR_M 0x3000000000000000ull 306#define XCT_MACRX_RR_NORES 0x0000000000000000ull 307#define XCT_MACRX_RR_8BRES 0x1000000000000000ull 308#define XCT_MACRX_O 0x0400000000000000ull 309#define XCT_MACRX_E 0x0200000000000000ull 310#define XCT_MACRX_FF 0x0100000000000000ull 311#define XCT_MACRX_PF 0x0080000000000000ull 312#define XCT_MACRX_OB 0x0040000000000000ull 313#define XCT_MACRX_OD 0x0020000000000000ull 314#define XCT_MACRX_FS 0x0010000000000000ull 315#define XCT_MACRX_NB_M 0x000fc00000000000ull 316#define XCT_MACRX_NB_S 46ULL 317#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \ 318 XCT_MACRX_NB_M) 319#define XCT_MACRX_LLEN_M 0x00003fff00000000ull 320#define XCT_MACRX_LLEN_S 32ULL 321#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \ 322 XCT_MACRX_LLEN_M) 323#define XCT_MACRX_CRC 0x0000000080000000ull 324#define XCT_MACRX_LEN_M 0x0000000060000000ull 325#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull 326#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull 327#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull 328#define XCT_MACRX_CAST_M 0x0000000018000000ull 329#define XCT_MACRX_CAST_UNI 0x0000000000000000ull 330#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull 331#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull 332#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull 333#define XCT_MACRX_VLC_M 0x0000000006000000ull 334#define XCT_MACRX_FM 0x0000000001000000ull 335#define XCT_MACRX_HTY_M 0x0000000000c00000ull 336#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull 337#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull 338#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull 339#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull 340#define XCT_MACRX_IPP_M 0x00000000003f0000ull 341#define XCT_MACRX_IPP_S 16 342#define XCT_MACRX_CSUM_M 0x000000000000ffffull 343#define XCT_MACRX_CSUM_S 0 344 345#define XCT_PTR_T 0x8000000000000000ull 346#define XCT_PTR_LEN_M 0x7ffff00000000000ull 347#define XCT_PTR_LEN_S 44 348#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ 349 XCT_PTR_LEN_M) 350#define XCT_PTR_ADDR_M 0x00000fffffffffffull 351#define XCT_PTR_ADDR_S 0 352#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ 353 XCT_PTR_ADDR_M) 354 355/* Receive interface 8byte result fields */ 356#define XCT_RXRES_8B_L4O_M 0xff00000000000000ull 357#define XCT_RXRES_8B_L4O_S 56 358#define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull 359#define XCT_RXRES_8B_RULE_S 40 360#define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull 361#define XCT_RXRES_8B_EVAL_S 24 362#define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull 363#define XCT_RXRES_8B_HASH_M 0x00000000000fffffull 364#define XCT_RXRES_8B_HASH_S 0 365 366/* Receive interface buffer fields */ 367#define XCT_RXB_LEN_M 0x0ffff00000000000ull 368#define XCT_RXB_LEN_S 44 369#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \ 370 XCT_RXB_LEN_M) 371#define XCT_RXB_ADDR_M 0x00000fffffffffffull 372#define XCT_RXB_ADDR_S 0 373#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \ 374 XCT_RXB_ADDR_M) 375 376/* Copy descriptor fields */ 377#define XCT_COPY_T 0x8000000000000000ull 378#define XCT_COPY_ST 0x4000000000000000ull 379#define XCT_COPY_RR_M 0x3000000000000000ull 380#define XCT_COPY_RR_NORES 0x0000000000000000ull 381#define XCT_COPY_RR_8BRES 0x1000000000000000ull 382#define XCT_COPY_RR_24BRES 0x2000000000000000ull 383#define XCT_COPY_RR_40BRES 0x3000000000000000ull 384#define XCT_COPY_I 0x0800000000000000ull 385#define XCT_COPY_O 0x0400000000000000ull 386#define XCT_COPY_E 0x0200000000000000ull 387#define XCT_COPY_STY_ZERO 0x01c0000000000000ull 388#define XCT_COPY_DTY_PREF 0x0038000000000000ull 389#define XCT_COPY_LLEN_M 0x0007ffff00000000ull 390#define XCT_COPY_LLEN_S 32 391#define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \ 392 XCT_COPY_LLEN_M) 393#define XCT_COPY_SE 0x0000000000000001ull 394 395/* Function descriptor fields */ 396#define XCT_FUN_T 0x8000000000000000ull 397#define XCT_FUN_ST 0x4000000000000000ull 398#define XCT_FUN_RR_M 0x3000000000000000ull 399#define XCT_FUN_RR_NORES 0x0000000000000000ull 400#define XCT_FUN_RR_8BRES 0x1000000000000000ull 401#define XCT_FUN_RR_24BRES 0x2000000000000000ull 402#define XCT_FUN_RR_40BRES 0x3000000000000000ull 403#define XCT_FUN_I 0x0800000000000000ull 404#define XCT_FUN_O 0x0400000000000000ull 405#define XCT_FUN_E 0x0200000000000000ull 406#define XCT_FUN_FUN_M 0x01c0000000000000ull 407#define XCT_FUN_FUN_S 54 408#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M) 409#define XCT_FUN_CRM_M 0x0038000000000000ull 410#define XCT_FUN_CRM_NOP 0x0000000000000000ull 411#define XCT_FUN_CRM_SIG 0x0008000000000000ull 412#define XCT_FUN_LLEN_M 0x0007ffff00000000ull 413#define XCT_FUN_LLEN_S 32 414#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M) 415#define XCT_FUN_SHL_M 0x00000000f8000000ull 416#define XCT_FUN_SHL_S 27 417#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M) 418#define XCT_FUN_CHL_M 0x0000000007c00000ull 419#define XCT_FUN_HSZ_M 0x00000000003c0000ull 420#define XCT_FUN_ALG_M 0x0000000000038000ull 421#define XCT_FUN_HP 0x0000000000004000ull 422#define XCT_FUN_BCM_M 0x0000000000003800ull 423#define XCT_FUN_BCP_M 0x0000000000000600ull 424#define XCT_FUN_SIG_M 0x00000000000001f0ull 425#define XCT_FUN_SIG_TCP4 0x0000000000000140ull 426#define XCT_FUN_SIG_TCP6 0x0000000000000150ull 427#define XCT_FUN_SIG_UDP4 0x0000000000000160ull 428#define XCT_FUN_SIG_UDP6 0x0000000000000170ull 429#define XCT_FUN_A 0x0000000000000008ull 430#define XCT_FUN_C 0x0000000000000004ull 431#define XCT_FUN_AL2 0x0000000000000002ull 432#define XCT_FUN_SE 0x0000000000000001ull 433 434/* Function descriptor 8byte result fields */ 435#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull 436#define XCT_FUNRES_8B_CS_S 32 437#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull 438#define XCT_FUNRES_8B_CRC_S 0 439 440/* Control descriptor fields */ 441#define CTRL_CMD_T 0x8000000000000000ull 442#define CTRL_CMD_META_EVT 0x2000000000000000ull 443#define CTRL_CMD_O 0x0400000000000000ull 444#define CTRL_CMD_ETYPE_M 0x0038000000000000ull 445#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull 446#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull 447#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull 448#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull 449#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull 450#define CTRL_CMD_REG_M 0x000000000000007full 451#define CTRL_CMD_REG_S 0 452#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \ 453 CTRL_CMD_REG_M) 454 455 456 457/* Prototypes for the shared DMA functions in the platform code. */ 458 459/* DMA TX Channel type. Right now only limitations used are event types 0/1, 460 * for event-triggered DMA transactions. 461 */ 462 463enum pasemi_dmachan_type { 464 RXCHAN = 0, /* Any RX chan */ 465 TXCHAN = 1, /* Any TX chan */ 466 TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */ 467 TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */ 468}; 469 470struct pasemi_dmachan { 471 int chno; /* Channel number */ 472 enum pasemi_dmachan_type chan_type; /* TX / RX */ 473 u64 *status; /* Ptr to cacheable status */ 474 int irq; /* IRQ used by channel */ 475 unsigned int ring_size; /* size of allocated ring */ 476 dma_addr_t ring_dma; /* DMA address for ring */ 477 u64 *ring_virt; /* Virt address for ring */ 478 void *priv; /* Ptr to start of client struct */ 479}; 480 481/* Read/write the different registers in the I/O Bridge, Ethernet 482 * and DMA Controller 483 */ 484extern unsigned int pasemi_read_iob_reg(unsigned int reg); 485extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val); 486 487extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg); 488extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val); 489 490extern unsigned int pasemi_read_dma_reg(unsigned int reg); 491extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val); 492 493/* Channel management routines */ 494 495extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, 496 int total_size, int offset); 497extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan); 498 499extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, 500 const u32 cmdsta); 501extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan); 502 503/* Common routines to allocate rings and buffers */ 504 505extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size); 506extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan); 507 508extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, 509 dma_addr_t *handle); 510extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, 511 dma_addr_t *handle); 512 513/* Routines to allocate flags (events) for channel synchronization */ 514extern int pasemi_dma_alloc_flag(void); 515extern void pasemi_dma_free_flag(int flag); 516extern void pasemi_dma_set_flag(int flag); 517extern void pasemi_dma_clear_flag(int flag); 518 519/* Routines to allocate function engines */ 520extern int pasemi_dma_alloc_fun(void); 521extern void pasemi_dma_free_fun(int fun); 522 523/* Initialize the library, must be called before any other functions */ 524extern int pasemi_dma_init(void); 525 526#endif /* ASM_PASEMI_DMA_H */ 527