1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_PARISC_ROPES_H_ 3#define _ASM_PARISC_ROPES_H_ 4 5#include <asm/parisc-device.h> 6 7#ifdef CONFIG_64BIT 8/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */ 9#define ZX1_SUPPORT 10#endif 11 12#ifdef CONFIG_PROC_FS 13/* depends on proc fs support. But costs CPU performance */ 14#undef SBA_COLLECT_STATS 15#endif 16 17/* 18** The number of pdir entries to "free" before issuing 19** a read to PCOM register to flush out PCOM writes. 20** Interacts with allocation granularity (ie 4 or 8 entries 21** allocated and free'd/purged at a time might make this 22** less interesting). 23*/ 24#define DELAYED_RESOURCE_CNT 16 25 26#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */ 27#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 28 29struct ioc { 30 void __iomem *ioc_hpa; /* I/O MMU base address */ 31 char *res_map; /* resource map, bit == pdir entry */ 32 __le64 *pdir_base; /* physical base address */ 33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */ 34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */ 35#ifdef ZX1_SUPPORT 36 unsigned long iovp_mask; /* help convert IOVA to IOVP */ 37#endif 38 unsigned long *res_hint; /* next avail IOVP - circular search */ 39 spinlock_t res_lock; 40 unsigned int res_bitshift; /* from the LEFT! */ 41 unsigned int res_size; /* size of resource map in bytes */ 42#ifdef SBA_HINT_SUPPORT 43/* FIXME : DMA HINTs not used */ 44 unsigned long hint_mask_pdir; /* bits used for DMA hints */ 45 unsigned int hint_shift_pdir; 46#endif 47#if DELAYED_RESOURCE_CNT > 0 48 int saved_cnt; 49 struct sba_dma_pair { 50 dma_addr_t iova; 51 size_t size; 52 } saved[DELAYED_RESOURCE_CNT]; 53#endif 54 55#ifdef SBA_COLLECT_STATS 56#define SBA_SEARCH_SAMPLE 0x100 57 unsigned long avg_search[SBA_SEARCH_SAMPLE]; 58 unsigned long avg_idx; /* current index into avg_search */ 59 unsigned long used_pages; 60 unsigned long msingle_calls; 61 unsigned long msingle_pages; 62 unsigned long msg_calls; 63 unsigned long msg_pages; 64 unsigned long usingle_calls; 65 unsigned long usingle_pages; 66 unsigned long usg_calls; 67 unsigned long usg_pages; 68#endif 69 /* STUFF We don't need in performance path */ 70 unsigned int pdir_size; /* in bytes, determined by IOV Space size */ 71}; 72 73struct sba_device { 74 struct sba_device *next; /* list of SBA's in system */ 75 struct parisc_device *dev; /* dev found in bus walk */ 76 const char *name; 77 void __iomem *sba_hpa; /* base address */ 78 spinlock_t sba_lock; 79 unsigned int flags; /* state/functionality enabled */ 80 unsigned int hw_rev; /* HW revision of chip */ 81 82 struct resource chip_resv; /* MMIO reserved for chip */ 83 struct resource iommu_resv; /* MMIO reserved for iommu */ 84 85 unsigned int num_ioc; /* number of on-board IOC's */ 86 struct ioc ioc[MAX_IOC]; 87}; 88 89/* list of SBA's in system, see drivers/parisc/sba_iommu.c */ 90extern struct sba_device *sba_list; 91 92#define ASTRO_RUNWAY_PORT 0x582 93#define IKE_MERCED_PORT 0x803 94#define REO_MERCED_PORT 0x804 95#define REOG_MERCED_PORT 0x805 96#define PLUTO_MCKINLEY_PORT 0x880 97 98static inline int IS_ASTRO(struct parisc_device *d) { 99 return d->id.hversion == ASTRO_RUNWAY_PORT; 100} 101 102static inline int IS_IKE(struct parisc_device *d) { 103 return d->id.hversion == IKE_MERCED_PORT; 104} 105 106static inline int IS_PLUTO(struct parisc_device *d) { 107 return d->id.hversion == PLUTO_MCKINLEY_PORT; 108} 109 110#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */ 111#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */ 112#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2) 113 114#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL 115 116#define SBA_AGPGART_COOKIE (__force __le64) 0x0000badbadc0ffeeULL 117 118#define SBA_FUNC_ID 0x0000 /* function id */ 119#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 120 121#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */ 122 123#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE) 124#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE) 125/* Ike's IOC's occupy functions 2 and 3 */ 126#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE) 127 128#define IOC_CTRL 0x8 /* IOC_CTRL offset */ 129#define IOC_CTRL_TC (1 << 0) /* TOC Enable */ 130#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */ 131#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */ 132#define IOC_CTRL_RM (1 << 8) /* Real Mode */ 133#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */ 134#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */ 135#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */ 136 137/* 138** Offsets into MBIB (Function 0 on Ike and hopefully Astro) 139** Firmware programs this stuff. Don't touch it. 140*/ 141#define LMMIO_DIRECT0_BASE 0x300 142#define LMMIO_DIRECT0_MASK 0x308 143#define LMMIO_DIRECT0_ROUTE 0x310 144 145#define LMMIO_DIST_BASE 0x360 146#define LMMIO_DIST_MASK 0x368 147#define LMMIO_DIST_ROUTE 0x370 148 149#define IOS_DIST_BASE 0x390 150#define IOS_DIST_MASK 0x398 151#define IOS_DIST_ROUTE 0x3A0 152 153#define IOS_DIRECT_BASE 0x3C0 154#define IOS_DIRECT_MASK 0x3C8 155#define IOS_DIRECT_ROUTE 0x3D0 156 157/* 158** Offsets into I/O TLB (Function 2 and 3 on Ike) 159*/ 160#define ROPE0_CTL 0x200 /* "regbus pci0" */ 161#define ROPE1_CTL 0x208 162#define ROPE2_CTL 0x210 163#define ROPE3_CTL 0x218 164#define ROPE4_CTL 0x220 165#define ROPE5_CTL 0x228 166#define ROPE6_CTL 0x230 167#define ROPE7_CTL 0x238 168 169#define IOC_ROPE0_CFG 0x500 /* pluto only */ 170#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ 171 172#define HF_ENABLE 0x40 173 174#define IOC_IBASE 0x300 /* IO TLB */ 175#define IOC_IMASK 0x308 176#define IOC_PCOM 0x310 177#define IOC_TCNFG 0x318 178#define IOC_PDIR_BASE 0x320 179 180/* 181** IOC supports 4/8/16/64KB page sizes (see TCNFG register) 182** It's safer (avoid memory corruption) to keep DMA page mappings 183** equivalently sized to VM PAGE_SIZE. 184** 185** We really can't avoid generating a new mapping for each 186** page since the Virtual Coherence Index has to be generated 187** and updated for each page. 188** 189** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse. 190*/ 191#define IOVP_SIZE PAGE_SIZE 192#define IOVP_SHIFT PAGE_SHIFT 193#define IOVP_MASK PAGE_MASK 194 195#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */ 196#define SBA_PERF_MASK1 0x718 197#define SBA_PERF_MASK2 0x730 198 199/* 200** Offsets into PCI Performance Counters (functions 12 and 13) 201** Controlled by PERF registers in function 2 & 3 respectively. 202*/ 203#define SBA_PERF_CNT1 0x200 204#define SBA_PERF_CNT2 0x208 205#define SBA_PERF_CNT3 0x210 206 207/* 208** lba_device: Per instance Elroy data structure 209*/ 210struct lba_device { 211 struct pci_hba_data hba; 212 213 spinlock_t lba_lock; 214 void *iosapic_obj; 215 216#ifdef CONFIG_64BIT 217 void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */ 218#endif 219 220 int flags; /* state/functionality enabled */ 221 int hw_rev; /* HW revision of chip */ 222}; 223 224#define ELROY_HVERS 0x782 225#define MERCURY_HVERS 0x783 226#define QUICKSILVER_HVERS 0x784 227 228static inline int IS_ELROY(struct parisc_device *d) { 229 return (d->id.hversion == ELROY_HVERS); 230} 231 232static inline int IS_MERCURY(struct parisc_device *d) { 233 return (d->id.hversion == MERCURY_HVERS); 234} 235 236static inline int IS_QUICKSILVER(struct parisc_device *d) { 237 return (d->id.hversion == QUICKSILVER_HVERS); 238} 239 240static inline int agp_mode_mercury(void __iomem *hpa) { 241 u64 bus_mode; 242 243 bus_mode = readl(hpa + 0x0620); 244 if (bus_mode & 1) 245 return 1; 246 247 return 0; 248} 249 250/* 251** I/O SAPIC init function 252** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC. 253** Call setup as part of per instance initialization. 254** (ie *not* init_module() function unless only one is present.) 255** fixup_irq is to initialize PCI IRQ line support and 256** virtualize pcidev->irq value. To be called by pci_fixup_bus(). 257*/ 258extern void *iosapic_register(unsigned long hpa, void __iomem *vaddr); 259extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev); 260 261#define LBA_FUNC_ID 0x0000 /* function id */ 262#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 263#define LBA_CAPABLE 0x0030 /* capabilities register */ 264 265#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */ 266#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */ 267 268#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */ 269#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */ 270#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */ 271 272#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */ 273#define LBA_ARB_PRI 0x0088 /* firmware sets this. */ 274#define LBA_ARB_MODE 0x0090 /* firmware sets this. */ 275#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */ 276 277#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */ 278 279#define LBA_STAT_CTL 0x0108 /* Status & Control */ 280#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */ 281#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */ 282#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */ 283#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ 284 285#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */ 286#define LBA_LMMIO_MASK 0x0208 287 288#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */ 289#define LBA_GMMIO_MASK 0x0218 290 291#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */ 292#define LBA_WLMMIO_MASK 0x0228 293 294#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */ 295#define LBA_WGMMIO_MASK 0x0238 296 297#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */ 298#define LBA_IOS_MASK 0x0248 299 300#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */ 301#define LBA_ELMMIO_MASK 0x0258 302 303#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */ 304#define LBA_EIOS_MASK 0x0268 305 306#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */ 307#define LBA_DMA_CTL 0x0278 /* firmware sets this */ 308 309#define LBA_IBASE 0x0300 /* SBA DMA support */ 310#define LBA_IMASK 0x0308 311 312/* FIXME: ignore DMA Hint stuff until we can measure performance */ 313#define LBA_HINT_CFG 0x0310 314#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */ 315 316#define LBA_BUS_MODE 0x0620 317 318/* ERROR regs are needed for config cycle kluges */ 319#define LBA_ERROR_CONFIG 0x0680 320#define LBA_SMART_MODE 0x20 321#define LBA_ERROR_STATUS 0x0688 322#define LBA_ROPE_CTL 0x06A0 323 324#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */ 325 326#endif /*_ASM_PARISC_ROPES_H_*/ 327