1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
5 * Copyright (C) 1999 SuSE GmbH
6 * Copyright (C) 2021 Helge Deller <deller@gmx.de>
7 */
8
9#ifndef _PARISC_ASSEMBLY_H
10#define _PARISC_ASSEMBLY_H
11
12#ifdef CONFIG_64BIT
13#define RP_OFFSET	16
14#define FRAME_SIZE	128
15#define CALLEE_REG_FRAME_SIZE	144
16#define REG_SZ		8
17#define ASM_ULONG_INSN	.dword
18#else	/* CONFIG_64BIT */
19#define RP_OFFSET	20
20#define FRAME_SIZE	64
21#define CALLEE_REG_FRAME_SIZE	128
22#define REG_SZ		4
23#define ASM_ULONG_INSN	.word
24#endif
25
26/* Frame alignment for 32- and 64-bit */
27#define FRAME_ALIGN     64
28
29#define CALLEE_FLOAT_FRAME_SIZE	80
30#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
31
32#ifdef CONFIG_PA20
33#define LDCW		ldcw,co
34#define BL		b,l
35# ifdef CONFIG_64BIT
36#  define PA_ASM_LEVEL	2.0w
37# else
38#  define PA_ASM_LEVEL	2.0
39# endif
40#else
41#define LDCW		ldcw
42#define BL		bl
43#define PA_ASM_LEVEL	1.1
44#endif
45
46/* Privilege level field in the rightmost two bits of the IA queues */
47#define PRIV_USER	3
48#define PRIV_KERNEL	0
49
50/* Space register used inside kernel */
51#define SR_KERNEL	0
52#define SR_TEMP1	1
53#define SR_TEMP2	2
54#define SR_USER		3
55
56#ifdef __ASSEMBLY__
57
58#ifdef CONFIG_64BIT
59#define LDREG	ldd
60#define STREG	std
61#define LDREGX  ldd,s
62#define LDREGM	ldd,mb
63#define STREGM	std,ma
64#define SHRREG	shrd
65#define SHLREG	shld
66#define ANDCM   andcm,*
67#define	COND(x)	* ## x
68#else	/* CONFIG_64BIT */
69#define LDREG	ldw
70#define STREG	stw
71#define LDREGX  ldwx,s
72#define LDREGM	ldwm
73#define STREGM	stwm
74#define SHRREG	shr
75#define SHLREG	shlw
76#define ANDCM   andcm
77#define COND(x)	x
78#endif
79
80#ifdef CONFIG_64BIT
81/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
82 * work around that for now... */
83	.level 2.0w
84#endif
85
86#include <asm/asm-offsets.h>
87#include <asm/page.h>
88#include <asm/types.h>
89
90#include <asm/asmregs.h>
91#include <asm/psw.h>
92
93	/*
94	 * We provide two versions of each macro to convert from physical
95	 * to virtual and vice versa. The "_r1" versions take one argument
96	 * register, but trashes r1 to do the conversion. The other
97	 * version takes two arguments: a src and destination register.
98	 * However, the source and destination registers can not be
99	 * the same register.
100	 *
101	 * We use add,l to avoid clobbering the C/B bits in the PSW.
102	 */
103
104	.macro  tophys  grvirt, grphys
105	ldil    L%(-__PAGE_OFFSET), \grphys
106	addl    \grvirt, \grphys, \grphys
107	.endm
108
109	.macro  tovirt  grphys, grvirt
110	ldil    L%(__PAGE_OFFSET), \grvirt
111	addl    \grphys, \grvirt, \grvirt
112	.endm
113
114	.macro  tophys_r1  gr
115	ldil    L%(-__PAGE_OFFSET), %r1
116	addl    \gr, %r1, \gr
117	.endm
118
119	.macro  tovirt_r1  gr
120	ldil    L%(__PAGE_OFFSET), %r1
121	addl    \gr, %r1, \gr
122	.endm
123
124	.macro delay value
125	ldil	L%\value, 1
126	ldo	R%\value(1), 1
127	addib,UV,n -1,1,.
128	addib,NUV,n -1,1,.+8
129	nop
130	.endm
131
132	.macro	debug value
133	.endm
134
135	.macro shlw r, sa, t
136	zdep	\r, 31-(\sa), 32-(\sa), \t
137	.endm
138
139	/* And the PA 2.0W shift left */
140	.macro shld r, sa, t
141	depd,z	\r, 63-(\sa), 64-(\sa), \t
142	.endm
143
144	/* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
145	.macro shr r, sa, t
146	extru \r, 31-(\sa), 32-(\sa), \t
147	.endm
148
149	/* pa20w version of shift right */
150	.macro shrd r, sa, t
151	extrd,u \r, 63-(\sa), 64-(\sa), \t
152	.endm
153
154	/* Extract unsigned for 32- and 64-bit
155	 * The extru instruction leaves the most significant 32 bits of the
156	 * target register in an undefined state on PA 2.0 systems. */
157	.macro extru_safe r, p, len, t
158#ifdef CONFIG_64BIT
159	extrd,u	\r, 32+(\p), \len, \t
160#else
161	extru	\r, \p, \len, \t
162#endif
163	.endm
164
165	/* The depi instruction leaves the most significant 32 bits of the
166	 * target register in an undefined state on PA 2.0 systems. */
167	.macro depi_safe i, p, len, t
168#ifdef CONFIG_64BIT
169	depdi	\i, 32+(\p), \len, \t
170#else
171	depi	\i, \p, \len, \t
172#endif
173	.endm
174
175	/* The depw instruction leaves the most significant 32 bits of the
176	 * target register in an undefined state on PA 2.0 systems. */
177	.macro dep_safe i, p, len, t
178#ifdef CONFIG_64BIT
179	depd	\i, 32+(\p), \len, \t
180#else
181	depw	\i, \p, \len, \t
182#endif
183	.endm
184
185	/* load 32-bit 'value' into 'reg' compensating for the ldil
186	 * sign-extension when running in wide mode.
187	 * WARNING!! neither 'value' nor 'reg' can be expressions
188	 * containing '.'!!!! */
189	.macro	load32 value, reg
190	ldil	L%\value, \reg
191	ldo	R%\value(\reg), \reg
192	.endm
193
194	.macro loadgp
195#ifdef CONFIG_64BIT
196	ldil		L%__gp, %r27
197	ldo		R%__gp(%r27), %r27
198#else
199	ldil		L%$global$, %r27
200	ldo		R%$global$(%r27), %r27
201#endif
202	.endm
203
204#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
205#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
206#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
207#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
208
209	.macro	save_general	regs
210	STREG %r1, PT_GR1 (\regs)
211	STREG %r2, PT_GR2 (\regs)
212	STREG %r3, PT_GR3 (\regs)
213	STREG %r4, PT_GR4 (\regs)
214	STREG %r5, PT_GR5 (\regs)
215	STREG %r6, PT_GR6 (\regs)
216	STREG %r7, PT_GR7 (\regs)
217	STREG %r8, PT_GR8 (\regs)
218	STREG %r9, PT_GR9 (\regs)
219	STREG %r10, PT_GR10(\regs)
220	STREG %r11, PT_GR11(\regs)
221	STREG %r12, PT_GR12(\regs)
222	STREG %r13, PT_GR13(\regs)
223	STREG %r14, PT_GR14(\regs)
224	STREG %r15, PT_GR15(\regs)
225	STREG %r16, PT_GR16(\regs)
226	STREG %r17, PT_GR17(\regs)
227	STREG %r18, PT_GR18(\regs)
228	STREG %r19, PT_GR19(\regs)
229	STREG %r20, PT_GR20(\regs)
230	STREG %r21, PT_GR21(\regs)
231	STREG %r22, PT_GR22(\regs)
232	STREG %r23, PT_GR23(\regs)
233	STREG %r24, PT_GR24(\regs)
234	STREG %r25, PT_GR25(\regs)
235	/* r26 is saved in get_stack and used to preserve a value across virt_map */
236	STREG %r27, PT_GR27(\regs)
237	STREG %r28, PT_GR28(\regs)
238	/* r29 is saved in get_stack and used to point to saved registers */
239	/* r30 stack pointer saved in get_stack */
240	STREG %r31, PT_GR31(\regs)
241	.endm
242
243	.macro	rest_general	regs
244	/* r1 used as a temp in rest_stack and is restored there */
245	LDREG PT_GR2 (\regs), %r2
246	LDREG PT_GR3 (\regs), %r3
247	LDREG PT_GR4 (\regs), %r4
248	LDREG PT_GR5 (\regs), %r5
249	LDREG PT_GR6 (\regs), %r6
250	LDREG PT_GR7 (\regs), %r7
251	LDREG PT_GR8 (\regs), %r8
252	LDREG PT_GR9 (\regs), %r9
253	LDREG PT_GR10(\regs), %r10
254	LDREG PT_GR11(\regs), %r11
255	LDREG PT_GR12(\regs), %r12
256	LDREG PT_GR13(\regs), %r13
257	LDREG PT_GR14(\regs), %r14
258	LDREG PT_GR15(\regs), %r15
259	LDREG PT_GR16(\regs), %r16
260	LDREG PT_GR17(\regs), %r17
261	LDREG PT_GR18(\regs), %r18
262	LDREG PT_GR19(\regs), %r19
263	LDREG PT_GR20(\regs), %r20
264	LDREG PT_GR21(\regs), %r21
265	LDREG PT_GR22(\regs), %r22
266	LDREG PT_GR23(\regs), %r23
267	LDREG PT_GR24(\regs), %r24
268	LDREG PT_GR25(\regs), %r25
269	LDREG PT_GR26(\regs), %r26
270	LDREG PT_GR27(\regs), %r27
271	LDREG PT_GR28(\regs), %r28
272	/* r29 points to register save area, and is restored in rest_stack */
273	/* r30 stack pointer restored in rest_stack */
274	LDREG PT_GR31(\regs), %r31
275	.endm
276
277	.macro	save_fp 	regs
278	fstd,ma  %fr0, 8(\regs)
279	fstd,ma	 %fr1, 8(\regs)
280	fstd,ma	 %fr2, 8(\regs)
281	fstd,ma	 %fr3, 8(\regs)
282	fstd,ma	 %fr4, 8(\regs)
283	fstd,ma	 %fr5, 8(\regs)
284	fstd,ma	 %fr6, 8(\regs)
285	fstd,ma	 %fr7, 8(\regs)
286	fstd,ma	 %fr8, 8(\regs)
287	fstd,ma	 %fr9, 8(\regs)
288	fstd,ma	%fr10, 8(\regs)
289	fstd,ma	%fr11, 8(\regs)
290	fstd,ma	%fr12, 8(\regs)
291	fstd,ma	%fr13, 8(\regs)
292	fstd,ma	%fr14, 8(\regs)
293	fstd,ma	%fr15, 8(\regs)
294	fstd,ma	%fr16, 8(\regs)
295	fstd,ma	%fr17, 8(\regs)
296	fstd,ma	%fr18, 8(\regs)
297	fstd,ma	%fr19, 8(\regs)
298	fstd,ma	%fr20, 8(\regs)
299	fstd,ma	%fr21, 8(\regs)
300	fstd,ma	%fr22, 8(\regs)
301	fstd,ma	%fr23, 8(\regs)
302	fstd,ma	%fr24, 8(\regs)
303	fstd,ma	%fr25, 8(\regs)
304	fstd,ma	%fr26, 8(\regs)
305	fstd,ma	%fr27, 8(\regs)
306	fstd,ma	%fr28, 8(\regs)
307	fstd,ma	%fr29, 8(\regs)
308	fstd,ma	%fr30, 8(\regs)
309	fstd	%fr31, 0(\regs)
310	.endm
311
312	.macro	rest_fp 	regs
313	fldd	0(\regs),	 %fr31
314	fldd,mb	-8(\regs),       %fr30
315	fldd,mb	-8(\regs),       %fr29
316	fldd,mb	-8(\regs),       %fr28
317	fldd,mb	-8(\regs),       %fr27
318	fldd,mb	-8(\regs),       %fr26
319	fldd,mb	-8(\regs),       %fr25
320	fldd,mb	-8(\regs),       %fr24
321	fldd,mb	-8(\regs),       %fr23
322	fldd,mb	-8(\regs),       %fr22
323	fldd,mb	-8(\regs),       %fr21
324	fldd,mb	-8(\regs),       %fr20
325	fldd,mb	-8(\regs),       %fr19
326	fldd,mb	-8(\regs),       %fr18
327	fldd,mb	-8(\regs),       %fr17
328	fldd,mb	-8(\regs),       %fr16
329	fldd,mb	-8(\regs),       %fr15
330	fldd,mb	-8(\regs),       %fr14
331	fldd,mb	-8(\regs),       %fr13
332	fldd,mb	-8(\regs),       %fr12
333	fldd,mb	-8(\regs),       %fr11
334	fldd,mb	-8(\regs),       %fr10
335	fldd,mb	-8(\regs),       %fr9
336	fldd,mb	-8(\regs),       %fr8
337	fldd,mb	-8(\regs),       %fr7
338	fldd,mb	-8(\regs),       %fr6
339	fldd,mb	-8(\regs),       %fr5
340	fldd,mb	-8(\regs),       %fr4
341	fldd,mb	-8(\regs),       %fr3
342	fldd,mb	-8(\regs),       %fr2
343	fldd,mb	-8(\regs),       %fr1
344	fldd,mb	-8(\regs),       %fr0
345	.endm
346
347	.macro	callee_save_float
348	fstd,ma	 %fr12,	8(%r30)
349	fstd,ma	 %fr13,	8(%r30)
350	fstd,ma	 %fr14,	8(%r30)
351	fstd,ma	 %fr15,	8(%r30)
352	fstd,ma	 %fr16,	8(%r30)
353	fstd,ma	 %fr17,	8(%r30)
354	fstd,ma	 %fr18,	8(%r30)
355	fstd,ma	 %fr19,	8(%r30)
356	fstd,ma	 %fr20,	8(%r30)
357	fstd,ma	 %fr21,	8(%r30)
358	.endm
359
360	.macro	callee_rest_float
361	fldd,mb	-8(%r30),   %fr21
362	fldd,mb	-8(%r30),   %fr20
363	fldd,mb	-8(%r30),   %fr19
364	fldd,mb	-8(%r30),   %fr18
365	fldd,mb	-8(%r30),   %fr17
366	fldd,mb	-8(%r30),   %fr16
367	fldd,mb	-8(%r30),   %fr15
368	fldd,mb	-8(%r30),   %fr14
369	fldd,mb	-8(%r30),   %fr13
370	fldd,mb	-8(%r30),   %fr12
371	.endm
372
373#ifdef CONFIG_64BIT
374	.macro	callee_save
375	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
376	mfctl	  %cr27, %r3
377	std	  %r4,	-136(%r30)
378	std	  %r5,	-128(%r30)
379	std	  %r6,	-120(%r30)
380	std	  %r7,	-112(%r30)
381	std	  %r8,	-104(%r30)
382	std	  %r9,	 -96(%r30)
383	std	 %r10,	 -88(%r30)
384	std	 %r11,	 -80(%r30)
385	std	 %r12,	 -72(%r30)
386	std	 %r13,	 -64(%r30)
387	std	 %r14,	 -56(%r30)
388	std	 %r15,	 -48(%r30)
389	std	 %r16,	 -40(%r30)
390	std	 %r17,	 -32(%r30)
391	std	 %r18,	 -24(%r30)
392	std	  %r3,	 -16(%r30)
393	.endm
394
395	.macro	callee_rest
396	ldd	 -16(%r30),    %r3
397	ldd	 -24(%r30),   %r18
398	ldd	 -32(%r30),   %r17
399	ldd	 -40(%r30),   %r16
400	ldd	 -48(%r30),   %r15
401	ldd	 -56(%r30),   %r14
402	ldd	 -64(%r30),   %r13
403	ldd	 -72(%r30),   %r12
404	ldd	 -80(%r30),   %r11
405	ldd	 -88(%r30),   %r10
406	ldd	 -96(%r30),    %r9
407	ldd	-104(%r30),    %r8
408	ldd	-112(%r30),    %r7
409	ldd	-120(%r30),    %r6
410	ldd	-128(%r30),    %r5
411	ldd	-136(%r30),    %r4
412	mtctl	%r3, %cr27
413	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
414	.endm
415
416#else /* ! CONFIG_64BIT */
417
418	.macro	callee_save
419	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
420	mfctl	 %cr27, %r3
421	stw	 %r4,	-124(%r30)
422	stw	 %r5,	-120(%r30)
423	stw	 %r6,	-116(%r30)
424	stw	 %r7,	-112(%r30)
425	stw	 %r8,	-108(%r30)
426	stw	 %r9,	-104(%r30)
427	stw	 %r10,	-100(%r30)
428	stw	 %r11,	 -96(%r30)
429	stw	 %r12,	 -92(%r30)
430	stw	 %r13,	 -88(%r30)
431	stw	 %r14,	 -84(%r30)
432	stw	 %r15,	 -80(%r30)
433	stw	 %r16,	 -76(%r30)
434	stw	 %r17,	 -72(%r30)
435	stw	 %r18,	 -68(%r30)
436	stw	  %r3,	 -64(%r30)
437	.endm
438
439	.macro	callee_rest
440	ldw	 -64(%r30),    %r3
441	ldw	 -68(%r30),   %r18
442	ldw	 -72(%r30),   %r17
443	ldw	 -76(%r30),   %r16
444	ldw	 -80(%r30),   %r15
445	ldw	 -84(%r30),   %r14
446	ldw	 -88(%r30),   %r13
447	ldw	 -92(%r30),   %r12
448	ldw	 -96(%r30),   %r11
449	ldw	-100(%r30),   %r10
450	ldw	-104(%r30),   %r9
451	ldw	-108(%r30),   %r8
452	ldw	-112(%r30),   %r7
453	ldw	-116(%r30),   %r6
454	ldw	-120(%r30),   %r5
455	ldw	-124(%r30),   %r4
456	mtctl	%r3, %cr27
457	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
458	.endm
459#endif /* ! CONFIG_64BIT */
460
461	.macro	save_specials	regs
462
463	SAVE_SP  (%sr0, PT_SR0 (\regs))
464	SAVE_SP  (%sr1, PT_SR1 (\regs))
465	SAVE_SP  (%sr2, PT_SR2 (\regs))
466	SAVE_SP  (%sr3, PT_SR3 (\regs))
467	SAVE_SP  (%sr4, PT_SR4 (\regs))
468	SAVE_SP  (%sr5, PT_SR5 (\regs))
469	SAVE_SP  (%sr6, PT_SR6 (\regs))
470
471	SAVE_CR  (%cr17, PT_IASQ0(\regs))
472	mtctl	 %r0,	%cr17
473	SAVE_CR  (%cr17, PT_IASQ1(\regs))
474
475	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
476	mtctl	 %r0,	%cr18
477	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
478
479#ifdef CONFIG_64BIT
480	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
481	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
482	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
483	 * we lose the 6th bit on a save/restore over interrupt.
484	 */
485	mfctl,w  %cr11, %r1
486	STREG    %r1, PT_SAR (\regs)
487#else
488	SAVE_CR  (%cr11, PT_SAR  (\regs))
489#endif
490	SAVE_CR  (%cr19, PT_IIR  (\regs))
491
492	/*
493	 * Code immediately following this macro (in intr_save) relies
494	 * on r8 containing ipsw.
495	 */
496	mfctl    %cr22, %r8
497	STREG    %r8,   PT_PSW(\regs)
498	.endm
499
500	.macro	rest_specials	regs
501
502	REST_SP  (%sr0, PT_SR0 (\regs))
503	REST_SP  (%sr1, PT_SR1 (\regs))
504	REST_SP  (%sr2, PT_SR2 (\regs))
505	REST_SP  (%sr3, PT_SR3 (\regs))
506	REST_SP  (%sr4, PT_SR4 (\regs))
507	REST_SP  (%sr5, PT_SR5 (\regs))
508	REST_SP  (%sr6, PT_SR6 (\regs))
509	REST_SP  (%sr7, PT_SR7 (\regs))
510
511	REST_CR	(%cr17, PT_IASQ0(\regs))
512	REST_CR	(%cr17, PT_IASQ1(\regs))
513
514	REST_CR	(%cr18, PT_IAOQ0(\regs))
515	REST_CR	(%cr18, PT_IAOQ1(\regs))
516
517	REST_CR (%cr11, PT_SAR	(\regs))
518
519	REST_CR	(%cr22, PT_PSW	(\regs))
520	.endm
521
522
523	/* First step to create a "relied upon translation"
524	 * See PA 2.0 Arch. page F-4 and F-5.
525	 *
526	 * The ssm was originally necessary due to a "PCxT bug".
527	 * But someone decided it needed to be added to the architecture
528	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
529	 * It's been carried forward into PA 2.0 Arch as well. :^(
530	 *
531	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
532	 * rsm/ssm prevents the ifetch unit from speculatively fetching
533	 * instructions past this line in the code stream.
534	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
535	 */
536	.macro	pcxt_ssm_bug
537	rsm	PSW_SM_I,%r0
538	nop	/* 1 */
539	nop	/* 2 */
540	nop	/* 3 */
541	nop	/* 4 */
542	nop	/* 5 */
543	nop	/* 6 */
544	nop	/* 7 */
545	.endm
546
547	/* Switch to virtual mapping, trashing only %r1 */
548	.macro  virt_map
549	/* pcxt_ssm_bug */
550	rsm	PSW_SM_I, %r0		/* barrier for "Relied upon Translation */
551	mtsp	%r0, %sr4
552	mtsp	%r0, %sr5
553	mtsp	%r0, %sr6
554	tovirt_r1 %r29
555	load32	KERNEL_PSW, %r1
556
557	rsm     PSW_SM_QUIET,%r0	/* second "heavy weight" ctl op */
558	mtctl	%r0, %cr17		/* Clear IIASQ tail */
559	mtctl	%r0, %cr17		/* Clear IIASQ head */
560	mtctl	%r1, %ipsw
561	load32	4f, %r1
562	mtctl	%r1, %cr18		/* Set IIAOQ tail */
563	ldo	4(%r1), %r1
564	mtctl	%r1, %cr18		/* Set IIAOQ head */
565	rfir
566	nop
5674:
568	.endm
569
570
571	/*
572	 * ASM_EXCEPTIONTABLE_ENTRY
573	 *
574	 * Creates an exception table entry.
575	 * Do not convert to a assembler macro. This won't work.
576	 */
577#define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr)	\
578	.section __ex_table,"aw"			!	\
579	.align 4					!	\
580	.word (fault_addr - .), (except_addr - .)	!	\
581	or %r0,%r0,%r0					!	\
582	.previous
583
584
585#endif /* __ASSEMBLY__ */
586#endif
587