1/*
2 * Code to handle IP32 IRQs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
10 */
11#include <linux/init.h>
12#include <linux/kernel_stat.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/bitops.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/random.h>
20#include <linux/sched.h>
21#include <linux/sched/debug.h>
22
23#include <asm/irq_cpu.h>
24#include <asm/mipsregs.h>
25#include <asm/signal.h>
26#include <asm/time.h>
27#include <asm/ip32/crime.h>
28#include <asm/ip32/mace.h>
29#include <asm/ip32/ip32_ints.h>
30
31#include "ip32-common.h"
32
33/* issue a PIO read to make sure no PIO writes are pending */
34static inline void flush_crime_bus(void)
35{
36	crime->control;
37}
38
39static inline void flush_mace_bus(void)
40{
41	mace->perif.ctrl.misc;
42}
43
44/*
45 * O2 irq map
46 *
47 * IP0 -> software (ignored)
48 * IP1 -> software (ignored)
49 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
50 * IP3 -> (irq1) X unknown
51 * IP4 -> (irq2) X unknown
52 * IP5 -> (irq3) X unknown
53 * IP6 -> (irq4) X unknown
54 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
55 *
56 * crime: (C)
57 *
58 * CRIME_INT_STAT 31:0:
59 *
60 * 0  ->  8  Video in 1
61 * 1  ->  9 Video in 2
62 * 2  -> 10  Video out
63 * 3  -> 11  Mace ethernet
64 * 4  -> S  SuperIO sub-interrupt
65 * 5  -> M  Miscellaneous sub-interrupt
66 * 6  -> A  Audio sub-interrupt
67 * 7  -> 15  PCI bridge errors
68 * 8  -> 16  PCI SCSI aic7xxx 0
69 * 9  -> 17 PCI SCSI aic7xxx 1
70 * 10 -> 18 PCI slot 0
71 * 11 -> 19 unused (PCI slot 1)
72 * 12 -> 20 unused (PCI slot 2)
73 * 13 -> 21 unused (PCI shared 0)
74 * 14 -> 22 unused (PCI shared 1)
75 * 15 -> 23 unused (PCI shared 2)
76 * 16 -> 24 GBE0 (E)
77 * 17 -> 25 GBE1 (E)
78 * 18 -> 26 GBE2 (E)
79 * 19 -> 27 GBE3 (E)
80 * 20 -> 28 CPU errors
81 * 21 -> 29 Memory errors
82 * 22 -> 30 RE empty edge (E)
83 * 23 -> 31 RE full edge (E)
84 * 24 -> 32 RE idle edge (E)
85 * 25 -> 33 RE empty level
86 * 26 -> 34 RE full level
87 * 27 -> 35 RE idle level
88 * 28 -> 36 unused (software 0) (E)
89 * 29 -> 37 unused (software 1) (E)
90 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
91 * 31 -> 39 VICE
92 *
93 * S, M, A: Use the MACE ISA interrupt register
94 * MACE_ISA_INT_STAT 31:0
95 *
96 * 0-7 -> 40-47 Audio
97 * 8 -> 48 RTC
98 * 9 -> 49 Keyboard
99 * 10 -> X Keyboard polled
100 * 11 -> 51 Mouse
101 * 12 -> X Mouse polled
102 * 13-15 -> 53-55 Count/compare timers
103 * 16-19 -> 56-59 Parallel (16 E)
104 * 20-25 -> 60-62 Serial 1 (22 E)
105 * 26-31 -> 66-71 Serial 2 (28 E)
106 *
107 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
108 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
109 * is quite different anyway.
110 */
111
112/*
113 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
114 * We get to split the register in half and do faster lookups.
115 */
116
117static uint64_t crime_mask;
118
119static inline void crime_enable_irq(struct irq_data *d)
120{
121	unsigned int bit = d->irq - CRIME_IRQ_BASE;
122
123	crime_mask |= 1 << bit;
124	crime->imask = crime_mask;
125}
126
127static inline void crime_disable_irq(struct irq_data *d)
128{
129	unsigned int bit = d->irq - CRIME_IRQ_BASE;
130
131	crime_mask &= ~(1 << bit);
132	crime->imask = crime_mask;
133	flush_crime_bus();
134}
135
136static struct irq_chip crime_level_interrupt = {
137	.name		= "IP32 CRIME",
138	.irq_mask	= crime_disable_irq,
139	.irq_unmask	= crime_enable_irq,
140};
141
142static void crime_edge_mask_and_ack_irq(struct irq_data *d)
143{
144	unsigned int bit = d->irq - CRIME_IRQ_BASE;
145	uint64_t crime_int;
146
147	/* Edge triggered interrupts must be cleared. */
148	crime_int = crime->hard_int;
149	crime_int &= ~(1 << bit);
150	crime->hard_int = crime_int;
151
152	crime_disable_irq(d);
153}
154
155static struct irq_chip crime_edge_interrupt = {
156	.name		= "IP32 CRIME",
157	.irq_ack	= crime_edge_mask_and_ack_irq,
158	.irq_mask	= crime_disable_irq,
159	.irq_mask_ack	= crime_edge_mask_and_ack_irq,
160	.irq_unmask	= crime_enable_irq,
161};
162
163/*
164 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
165 * as close to the source as possible.	This also means we can take the
166 * next chunk of the CRIME register in one piece.
167 */
168
169static unsigned long macepci_mask;
170
171static void enable_macepci_irq(struct irq_data *d)
172{
173	macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
174	mace->pci.control = macepci_mask;
175	crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
176	crime->imask = crime_mask;
177}
178
179static void disable_macepci_irq(struct irq_data *d)
180{
181	crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
182	crime->imask = crime_mask;
183	flush_crime_bus();
184	macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
185	mace->pci.control = macepci_mask;
186	flush_mace_bus();
187}
188
189static struct irq_chip ip32_macepci_interrupt = {
190	.name = "IP32 MACE PCI",
191	.irq_mask = disable_macepci_irq,
192	.irq_unmask = enable_macepci_irq,
193};
194
195/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
196 * CRIME register.
197 */
198
199#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
200				 MACEISA_AUDIO_SC_INT |		\
201				 MACEISA_AUDIO1_DMAT_INT |	\
202				 MACEISA_AUDIO1_OF_INT |	\
203				 MACEISA_AUDIO2_DMAT_INT |	\
204				 MACEISA_AUDIO2_MERR_INT |	\
205				 MACEISA_AUDIO3_DMAT_INT |	\
206				 MACEISA_AUDIO3_MERR_INT)
207#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
208				 MACEISA_KEYB_INT |		\
209				 MACEISA_KEYB_POLL_INT |	\
210				 MACEISA_MOUSE_INT |		\
211				 MACEISA_MOUSE_POLL_INT |	\
212				 MACEISA_TIMER0_INT |		\
213				 MACEISA_TIMER1_INT |		\
214				 MACEISA_TIMER2_INT)
215#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
216				 MACEISA_PAR_CTXA_INT |		\
217				 MACEISA_PAR_CTXB_INT |		\
218				 MACEISA_PAR_MERR_INT |		\
219				 MACEISA_SERIAL1_INT |		\
220				 MACEISA_SERIAL1_TDMAT_INT |	\
221				 MACEISA_SERIAL1_TDMAPR_INT |	\
222				 MACEISA_SERIAL1_TDMAME_INT |	\
223				 MACEISA_SERIAL1_RDMAT_INT |	\
224				 MACEISA_SERIAL1_RDMAOR_INT |	\
225				 MACEISA_SERIAL2_INT |		\
226				 MACEISA_SERIAL2_TDMAT_INT |	\
227				 MACEISA_SERIAL2_TDMAPR_INT |	\
228				 MACEISA_SERIAL2_TDMAME_INT |	\
229				 MACEISA_SERIAL2_RDMAT_INT |	\
230				 MACEISA_SERIAL2_RDMAOR_INT)
231
232static unsigned long maceisa_mask;
233
234static void enable_maceisa_irq(struct irq_data *d)
235{
236	unsigned int crime_int = 0;
237
238	pr_debug("maceisa enable: %u\n", d->irq);
239
240	switch (d->irq) {
241	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
242		crime_int = MACE_AUDIO_INT;
243		break;
244	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
245		crime_int = MACE_MISC_INT;
246		break;
247	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
248		crime_int = MACE_SUPERIO_INT;
249		break;
250	}
251	pr_debug("crime_int %08x enabled\n", crime_int);
252	crime_mask |= crime_int;
253	crime->imask = crime_mask;
254	maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
255	mace->perif.ctrl.imask = maceisa_mask;
256}
257
258static void disable_maceisa_irq(struct irq_data *d)
259{
260	unsigned int crime_int = 0;
261
262	maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
263	if (!(maceisa_mask & MACEISA_AUDIO_INT))
264		crime_int |= MACE_AUDIO_INT;
265	if (!(maceisa_mask & MACEISA_MISC_INT))
266		crime_int |= MACE_MISC_INT;
267	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
268		crime_int |= MACE_SUPERIO_INT;
269	crime_mask &= ~crime_int;
270	crime->imask = crime_mask;
271	flush_crime_bus();
272	mace->perif.ctrl.imask = maceisa_mask;
273	flush_mace_bus();
274}
275
276static void mask_and_ack_maceisa_irq(struct irq_data *d)
277{
278	unsigned long mace_int;
279
280	/* edge triggered */
281	mace_int = mace->perif.ctrl.istat;
282	mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
283	mace->perif.ctrl.istat = mace_int;
284
285	disable_maceisa_irq(d);
286}
287
288static struct irq_chip ip32_maceisa_level_interrupt = {
289	.name		= "IP32 MACE ISA",
290	.irq_mask	= disable_maceisa_irq,
291	.irq_unmask	= enable_maceisa_irq,
292};
293
294static struct irq_chip ip32_maceisa_edge_interrupt = {
295	.name		= "IP32 MACE ISA",
296	.irq_ack	= mask_and_ack_maceisa_irq,
297	.irq_mask	= disable_maceisa_irq,
298	.irq_mask_ack	= mask_and_ack_maceisa_irq,
299	.irq_unmask	= enable_maceisa_irq,
300};
301
302/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
303 * bits 0-3 and 7 in the CRIME register.
304 */
305
306static void enable_mace_irq(struct irq_data *d)
307{
308	unsigned int bit = d->irq - CRIME_IRQ_BASE;
309
310	crime_mask |= (1 << bit);
311	crime->imask = crime_mask;
312}
313
314static void disable_mace_irq(struct irq_data *d)
315{
316	unsigned int bit = d->irq - CRIME_IRQ_BASE;
317
318	crime_mask &= ~(1 << bit);
319	crime->imask = crime_mask;
320	flush_crime_bus();
321}
322
323static struct irq_chip ip32_mace_interrupt = {
324	.name = "IP32 MACE",
325	.irq_mask = disable_mace_irq,
326	.irq_unmask = enable_mace_irq,
327};
328
329static void ip32_unknown_interrupt(void)
330{
331	printk("Unknown interrupt occurred!\n");
332	printk("cp0_status: %08x\n", read_c0_status());
333	printk("cp0_cause: %08x\n", read_c0_cause());
334	printk("CRIME intr mask: %016lx\n", crime->imask);
335	printk("CRIME intr status: %016lx\n", crime->istat);
336	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
337	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
338	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
339	printk("MACE PCI control register: %08x\n", mace->pci.control);
340
341	printk("Register dump:\n");
342	show_regs(get_irq_regs());
343
344	printk("Please mail this report to linux-mips@vger.kernel.org\n");
345	printk("Spinning...");
346	while(1) ;
347}
348
349/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
350/* change this to loop over all edge-triggered irqs, exception masked out ones */
351static void ip32_irq0(void)
352{
353	uint64_t crime_int;
354	int irq = 0;
355
356	/*
357	 * Sanity check interrupt numbering enum.
358	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
359	 * chained.
360	 */
361	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
362	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
363
364	crime_int = crime->istat & crime_mask;
365
366	/* crime sometime delivers spurious interrupts, ignore them */
367	if (unlikely(crime_int == 0))
368		return;
369
370	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
371
372	if (crime_int & CRIME_MACEISA_INT_MASK) {
373		unsigned long mace_int = mace->perif.ctrl.istat;
374		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
375	}
376
377	pr_debug("*irq %u*\n", irq);
378	do_IRQ(irq);
379}
380
381static void ip32_irq1(void)
382{
383	ip32_unknown_interrupt();
384}
385
386static void ip32_irq2(void)
387{
388	ip32_unknown_interrupt();
389}
390
391static void ip32_irq3(void)
392{
393	ip32_unknown_interrupt();
394}
395
396static void ip32_irq4(void)
397{
398	ip32_unknown_interrupt();
399}
400
401static void ip32_irq5(void)
402{
403	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
404}
405
406asmlinkage void plat_irq_dispatch(void)
407{
408	unsigned int pending = read_c0_status() & read_c0_cause();
409
410	if (likely(pending & IE_IRQ0))
411		ip32_irq0();
412	else if (unlikely(pending & IE_IRQ1))
413		ip32_irq1();
414	else if (unlikely(pending & IE_IRQ2))
415		ip32_irq2();
416	else if (unlikely(pending & IE_IRQ3))
417		ip32_irq3();
418	else if (unlikely(pending & IE_IRQ4))
419		ip32_irq4();
420	else if (likely(pending & IE_IRQ5))
421		ip32_irq5();
422}
423
424void __init arch_init_irq(void)
425{
426	unsigned int irq;
427
428	/* Install our interrupt handler, then clear and disable all
429	 * CRIME and MACE interrupts. */
430	crime->imask = 0;
431	crime->hard_int = 0;
432	crime->soft_int = 0;
433	mace->perif.ctrl.istat = 0;
434	mace->perif.ctrl.imask = 0;
435
436	mips_cpu_irq_init();
437	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
438		switch (irq) {
439		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
440			irq_set_chip_and_handler_name(irq,
441						      &ip32_mace_interrupt,
442						      handle_level_irq,
443						      "level");
444			break;
445
446		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
447			irq_set_chip_and_handler_name(irq,
448						      &ip32_macepci_interrupt,
449						      handle_level_irq,
450						      "level");
451			break;
452
453		case CRIME_CPUERR_IRQ:
454		case CRIME_MEMERR_IRQ:
455			irq_set_chip_and_handler_name(irq,
456						      &crime_level_interrupt,
457						      handle_level_irq,
458						      "level");
459			break;
460
461		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
462		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
463		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
464		case CRIME_VICE_IRQ:
465			irq_set_chip_and_handler_name(irq,
466						      &crime_edge_interrupt,
467						      handle_edge_irq,
468						      "edge");
469			break;
470
471		case MACEISA_PARALLEL_IRQ:
472		case MACEISA_SERIAL1_TDMAPR_IRQ:
473		case MACEISA_SERIAL2_TDMAPR_IRQ:
474			irq_set_chip_and_handler_name(irq,
475						      &ip32_maceisa_edge_interrupt,
476						      handle_edge_irq,
477						      "edge");
478			break;
479
480		default:
481			irq_set_chip_and_handler_name(irq,
482						      &ip32_maceisa_level_interrupt,
483						      handle_level_irq,
484						      "level");
485			break;
486		}
487	}
488	if (request_irq(CRIME_MEMERR_IRQ, crime_memerr_intr, 0,
489			"CRIME memory error", NULL))
490		pr_err("Failed to register CRIME memory error interrupt\n");
491	if (request_irq(CRIME_CPUERR_IRQ, crime_cpuerr_intr, 0,
492			"CRIME CPU error", NULL))
493		pr_err("Failed to register CRIME CPU error interrupt\n");
494
495#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
496	change_c0_status(ST0_IM, ALLINTS);
497}
498