1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2016 Imagination Technologies
4 * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
5 */
6
7#ifndef __PROBES_COMMON_H
8#define __PROBES_COMMON_H
9
10#include <asm/inst.h>
11
12int __insn_is_compact_branch(union mips_instruction insn);
13
14static inline int __insn_has_delay_slot(const union mips_instruction insn)
15{
16	switch (insn.i_format.opcode) {
17	/*
18	 * jr and jalr are in r_format format.
19	 */
20	case spec_op:
21		switch (insn.r_format.func) {
22		case jalr_op:
23		case jr_op:
24			return 1;
25		}
26		break;
27
28	/*
29	 * This group contains:
30	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
31	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
32	 */
33	case bcond_op:
34		switch (insn.i_format.rt) {
35		case bltz_op:
36		case bltzl_op:
37		case bgez_op:
38		case bgezl_op:
39		case bltzal_op:
40		case bltzall_op:
41		case bgezal_op:
42		case bgezall_op:
43		case bposge32_op:
44			return 1;
45		}
46		break;
47
48	/*
49	 * These are unconditional and in j_format.
50	 */
51	case jal_op:
52	case j_op:
53	case beq_op:
54	case beql_op:
55	case bne_op:
56	case bnel_op:
57	case blez_op: /* not really i_format */
58	case blezl_op:
59	case bgtz_op:
60	case bgtzl_op:
61		return 1;
62
63	/*
64	 * And now the FPA/cp1 branch instructions.
65	 */
66	case cop1_op:
67#ifdef CONFIG_CPU_CAVIUM_OCTEON
68	case lwc2_op: /* This is bbit0 on Octeon */
69	case ldc2_op: /* This is bbit032 on Octeon */
70	case swc2_op: /* This is bbit1 on Octeon */
71	case sdc2_op: /* This is bbit132 on Octeon */
72#endif
73		return 1;
74	}
75
76	return 0;
77}
78
79#endif  /* __PROBES_COMMON_H */
80