1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2#include <dt-bindings/interrupt-controller/mips-gic.h>
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/clock/mt7621-clk.h>
5#include <dt-bindings/reset/mt7621-reset.h>
6
7/ {
8	compatible = "mediatek,mt7621-soc";
9
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			compatible = "mips,mips1004Kc";
19			reg = <0>;
20			device_type = "cpu";
21		};
22
23		cpu@1 {
24			compatible = "mips,mips1004Kc";
25			reg = <1>;
26			device_type = "cpu";
27		};
28	};
29
30	cpuintc: cpuintc {
31		compatible = "mti,cpu-interrupt-controller";
32
33		#address-cells = <0>;
34		#interrupt-cells = <1>;
35
36		interrupt-controller;
37	};
38
39	mmc_fixed_3v3: regulator-3v3 {
40		compatible = "regulator-fixed";
41
42		enable-active-high;
43
44		regulator-always-on;
45		regulator-max-microvolt = <3300000>;
46		regulator-min-microvolt = <3300000>;
47		regulator-name = "mmc_power";
48	};
49
50	mmc_fixed_1v8_io: regulator-1v8 {
51		compatible = "regulator-fixed";
52
53		enable-active-high;
54
55		regulator-always-on;
56		regulator-max-microvolt = <1800000>;
57		regulator-min-microvolt = <1800000>;
58		regulator-name = "mmc_io";
59	};
60
61	pinctrl: pinctrl {
62		compatible = "ralink,mt7621-pinctrl";
63
64		i2c_pins: i2c0-pins {
65			pinmux {
66				groups = "i2c";
67				function = "i2c";
68			};
69		};
70
71		mdio_pins: mdio0-pins {
72			pinmux {
73				groups = "mdio";
74				function = "mdio";
75			};
76		};
77
78		nand_pins: nand0-pins {
79			sdhci-pinmux {
80				groups = "sdhci";
81				function = "nand2";
82			};
83
84			spi-pinmux {
85				groups = "spi";
86				function = "nand1";
87			};
88		};
89
90		pcie_pins: pcie0-pins {
91			pinmux {
92				groups = "pcie";
93				function = "gpio";
94			};
95		};
96
97		rgmii1_pins: rgmii1-pins {
98			pinmux {
99				groups = "rgmii1";
100				function = "rgmii1";
101			};
102		};
103
104		rgmii2_pins: rgmii2-pins {
105			pinmux {
106				groups = "rgmii2";
107				function = "rgmii2";
108			};
109		};
110
111		sdhci_pins: sdhci0-pins {
112			pinmux {
113				groups = "sdhci";
114				function = "sdhci";
115			};
116		};
117
118		spi_pins: spi0-pins {
119			pinmux {
120				groups = "spi";
121				function = "spi";
122			};
123		};
124
125		uart1_pins: uart1-pins {
126			pinmux {
127				groups = "uart1";
128				function = "uart1";
129			};
130		};
131
132		uart2_pins: uart2-pins {
133			pinmux {
134				groups = "uart2";
135				function = "uart2";
136			};
137		};
138
139		uart3_pins: uart3-pins {
140			pinmux {
141				groups = "uart3";
142				function = "uart3";
143			};
144		};
145	};
146
147	palmbus: palmbus@1e000000 {
148		compatible = "palmbus";
149		reg = <0x1e000000 0x100000>;
150		ranges = <0x0 0x1e000000 0x0fffff>;
151
152		#address-cells = <1>;
153		#size-cells = <1>;
154
155		sysc: syscon@0 {
156			compatible = "mediatek,mt7621-sysc", "syscon";
157			reg = <0x0 0x100>;
158
159			#clock-cells = <1>;
160			#reset-cells = <1>;
161
162			clock-output-names = "xtal", "cpu", "bus",
163					     "50m", "125m", "150m",
164					     "250m", "270m";
165
166			ralink,memctl = <&memc>;
167		};
168
169		wdt: watchdog@100 {
170			compatible = "mediatek,mt7621-wdt";
171			reg = <0x100 0x100>;
172			mediatek,sysctl = <&sysc>;
173		};
174
175		gpio: gpio@600 {
176			compatible = "mediatek,mt7621-gpio";
177			reg = <0x600 0x100>;
178
179			#gpio-cells = <2>;
180			#interrupt-cells = <2>;
181
182			gpio-controller;
183			gpio-ranges = <&pinctrl 0 0 95>;
184
185			interrupt-controller;
186			interrupt-parent = <&gic>;
187			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
188		};
189
190		i2c: i2c@900 {
191			compatible = "mediatek,mt7621-i2c";
192			reg = <0x900 0x100>;
193
194			#address-cells = <1>;
195			#size-cells = <0>;
196
197			clocks = <&sysc MT7621_CLK_I2C>;
198			clock-names = "i2c";
199
200			pinctrl-names = "default";
201			pinctrl-0 = <&i2c_pins>;
202
203			resets = <&sysc MT7621_RST_I2C>;
204			reset-names = "i2c";
205
206			status = "disabled";
207		};
208
209		memc: memory-controller@5000 {
210			compatible = "mediatek,mt7621-memc", "syscon";
211			reg = <0x5000 0x1000>;
212		};
213
214		serial0: serial@c00 {
215			compatible = "ns16550a";
216			reg = <0xc00 0x100>;
217
218			reg-io-width = <4>;
219			reg-shift = <2>;
220
221			clocks = <&sysc MT7621_CLK_UART1>;
222
223			interrupt-parent = <&gic>;
224			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
225
226			no-loopback-test;
227
228			pinctrl-names = "default";
229			pinctrl-0 = <&uart1_pins>;
230		};
231
232		serial1: serial@d00 {
233			compatible = "ns16550a";
234			reg = <0xd00 0x100>;
235
236			reg-io-width = <4>;
237			reg-shift = <2>;
238
239			clocks = <&sysc MT7621_CLK_UART2>;
240
241			interrupt-parent = <&gic>;
242			interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
243
244			no-loopback-test;
245
246			pinctrl-names = "default";
247			pinctrl-0 = <&uart2_pins>;
248
249			status = "disabled";
250		};
251
252		serial2: serial@e00 {
253			compatible = "ns16550a";
254			reg = <0xe00 0x100>;
255
256			reg-io-width = <4>;
257			reg-shift = <2>;
258
259			clocks = <&sysc MT7621_CLK_UART3>;
260
261			interrupt-parent = <&gic>;
262			interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
263
264			no-loopback-test;
265
266			pinctrl-names = "default";
267			pinctrl-0 = <&uart3_pins>;
268
269			status = "disabled";
270		};
271
272		spi0: spi@b00 {
273			compatible = "ralink,mt7621-spi";
274			reg = <0xb00 0x100>;
275
276			#address-cells = <1>;
277			#size-cells = <0>;
278
279			clock-names = "spi";
280			clocks = <&sysc MT7621_CLK_SPI>;
281
282			pinctrl-names = "default";
283			pinctrl-0 = <&spi_pins>;
284
285			reset-names = "spi";
286			resets = <&sysc MT7621_RST_SPI>;
287
288			status = "disabled";
289		};
290	};
291
292	mmc: mmc@1e130000 {
293		compatible = "mediatek,mt7620-mmc";
294		reg = <0x1e130000 0x4000>;
295
296		bus-width = <4>;
297
298		cap-mmc-highspeed;
299		cap-sd-highspeed;
300
301		clocks = <&sysc MT7621_CLK_SHXC>,
302			 <&sysc MT7621_CLK_50M>;
303		clock-names = "source", "hclk";
304
305		disable-wp;
306
307		interrupt-parent = <&gic>;
308		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
309
310		max-frequency = <48000000>;
311
312		pinctrl-names = "default", "state_uhs";
313		pinctrl-0 = <&sdhci_pins>;
314		pinctrl-1 = <&sdhci_pins>;
315
316		vmmc-supply = <&mmc_fixed_3v3>;
317		vqmmc-supply = <&mmc_fixed_1v8_io>;
318
319		status = "disabled";
320	};
321
322	usb: usb@1e1c0000 {
323		compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
324		reg = <0x1e1c0000 0x1000
325		       0x1e1d0700 0x0100>;
326		reg-names = "mac", "ippc";
327
328		#address-cells = <1>;
329		#size-cells = <0>;
330
331		clocks = <&sysc MT7621_CLK_XTAL>;
332		clock-names = "sys_ck";
333
334		interrupt-parent = <&gic>;
335		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
336	};
337
338	gic: interrupt-controller@1fbc0000 {
339		compatible = "mti,gic";
340		reg = <0x1fbc0000 0x2000>;
341
342		#interrupt-cells = <3>;
343		interrupt-controller;
344
345		mti,reserved-cpu-vectors = <7>;
346
347		timer {
348			compatible = "mti,gic-timer";
349			clocks = <&sysc MT7621_CLK_CPU>;
350			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
351		};
352	};
353
354	cpc: cpc@1fbf0000 {
355		compatible = "mti,mips-cpc";
356		reg = <0x1fbf0000 0x8000>;
357	};
358
359	cdmm: cdmm@1fbf8000 {
360		compatible = "mti,mips-cdmm";
361		reg = <0x1fbf8000 0x8000>;
362	};
363
364	ethernet: ethernet@1e100000 {
365		compatible = "mediatek,mt7621-eth";
366		reg = <0x1e100000 0x10000>;
367
368		#address-cells = <1>;
369		#size-cells = <0>;
370
371		clock-names = "fe", "ethif";
372		clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
373
374		interrupt-parent = <&gic>;
375		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
376
377		pinctrl-names = "default";
378		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
379
380		reset-names = "fe", "eth";
381		resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
382
383		mediatek,ethsys = <&sysc>;
384
385		mdio: mdio-bus {
386			#address-cells = <1>;
387			#size-cells = <0>;
388
389			switch0: switch@1f {
390				compatible = "mediatek,mt7621";
391				reg = <0x1f>;
392
393				#interrupt-cells = <1>;
394				interrupt-controller;
395				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
396
397				reset-names = "mcm";
398				resets = <&sysc MT7621_RST_MCM>;
399
400				mediatek,mcm;
401
402				ports {
403					#address-cells = <1>;
404					#size-cells = <0>;
405
406					port@0 {
407						reg = <0>;
408						label = "swp0";
409						status = "disabled";
410					};
411
412					port@1 {
413						reg = <1>;
414						label = "swp1";
415						status = "disabled";
416					};
417
418					port@2 {
419						reg = <2>;
420						label = "swp2";
421						status = "disabled";
422					};
423
424					port@3 {
425						reg = <3>;
426						label = "swp3";
427						status = "disabled";
428					};
429
430					port@4 {
431						reg = <4>;
432						label = "swp4";
433						status = "disabled";
434					};
435
436					port@5 {
437						reg = <5>;
438
439						ethernet = <&gmac1>;
440						phy-mode = "rgmii";
441
442						fixed-link {
443							full-duplex;
444							pause;
445							speed = <1000>;
446						};
447					};
448
449					port@6 {
450						reg = <6>;
451
452						ethernet = <&gmac0>;
453						phy-mode = "trgmii";
454
455						fixed-link {
456							full-duplex;
457							pause;
458							speed = <1000>;
459						};
460					};
461				};
462			};
463		};
464
465		gmac0: mac@0 {
466			compatible = "mediatek,eth-mac";
467			reg = <0>;
468
469			phy-mode = "trgmii";
470
471			fixed-link {
472				full-duplex;
473				pause;
474				speed = <1000>;
475			};
476		};
477
478		gmac1: mac@1 {
479			compatible = "mediatek,eth-mac";
480			reg = <1>;
481
482			phy-mode = "rgmii";
483
484			fixed-link {
485				full-duplex;
486				pause;
487				speed = <1000>;
488			};
489		};
490
491	};
492
493	pcie: pcie@1e140000 {
494		compatible = "mediatek,mt7621-pci";
495		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
496		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
497		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
498		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
499		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
500			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
501
502		#address-cells = <3>;
503		#interrupt-cells = <1>;
504		#size-cells = <2>;
505
506		device_type = "pci";
507
508		interrupt-map-mask = <0xf800 0 0 0>;
509		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED  4 IRQ_TYPE_LEVEL_HIGH>,
510				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
511				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
512
513		pinctrl-names = "default";
514		pinctrl-0 = <&pcie_pins>;
515
516		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
517
518		status = "disabled";
519
520		pcie@0,0 {
521			reg = <0x0000 0 0 0 0>;
522			ranges;
523
524			#address-cells = <3>;
525			#interrupt-cells = <1>;
526			#size-cells = <2>;
527
528			clocks = <&sysc MT7621_CLK_PCIE0>;
529
530			device_type = "pci";
531
532			interrupt-map-mask = <0 0 0 0>;
533			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
534
535			phy-names = "pcie-phy0";
536			phys = <&pcie0_phy 1>;
537
538			resets = <&sysc MT7621_RST_PCIE0>;
539		};
540
541		pcie@1,0 {
542			reg = <0x0800 0 0 0 0>;
543			ranges;
544
545			#address-cells = <3>;
546			#interrupt-cells = <1>;
547			#size-cells = <2>;
548
549			clocks = <&sysc MT7621_CLK_PCIE1>;
550
551			device_type = "pci";
552
553			interrupt-map-mask = <0 0 0 0>;
554			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
555
556			phy-names = "pcie-phy1";
557			phys = <&pcie0_phy 1>;
558
559			resets = <&sysc MT7621_RST_PCIE1>;
560		};
561
562		pcie@2,0 {
563			reg = <0x1000 0 0 0 0>;
564			ranges;
565
566			#address-cells = <3>;
567			#interrupt-cells = <1>;
568			#size-cells = <2>;
569
570			clocks = <&sysc MT7621_CLK_PCIE2>;
571
572			device_type = "pci";
573
574			interrupt-map-mask = <0 0 0 0>;
575			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
576
577			phy-names = "pcie-phy2";
578			phys = <&pcie2_phy 0>;
579
580			resets = <&sysc MT7621_RST_PCIE2>;
581		};
582	};
583
584	pcie0_phy: pcie-phy@1e149000 {
585		compatible = "mediatek,mt7621-pci-phy";
586		reg = <0x1e149000 0x0700>;
587
588		#phy-cells = <1>;
589
590		clocks = <&sysc MT7621_CLK_XTAL>;
591	};
592
593	pcie2_phy: pcie-phy@1e14a000 {
594		compatible = "mediatek,mt7621-pci-phy";
595		reg = <0x1e14a000 0x0700>;
596
597		#phy-cells = <1>;
598
599		clocks = <&sysc MT7621_CLK_XTAL>;
600	};
601};
602