1/*
2 *  linux/arch/m68k/kernel/traps.c
3 *
4 *  Copyright (C) 1993, 1994 by Hamish Macdonald
5 *
6 *  68040 fixes by Michael Rausch
7 *  68040 fixes by Martin Apel
8 *  68040 fixes and writeback by Richard Zidlicky
9 *  68060 fixes by Roman Hodek
10 *  68060 fixes by Jesper Skov
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License.  See the file COPYING in the main directory of this archive
14 * for more details.
15 */
16
17/*
18 * Sets up all exception vectors
19 */
20
21#include <linux/sched.h>
22#include <linux/sched/debug.h>
23#include <linux/signal.h>
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/user.h>
28#include <linux/string.h>
29#include <linux/linkage.h>
30#include <linux/init.h>
31#include <linux/ptrace.h>
32#include <linux/kallsyms.h>
33#include <linux/extable.h>
34
35#include <asm/setup.h>
36#include <asm/fpu.h>
37#include <linux/uaccess.h>
38#include <asm/traps.h>
39#include <asm/machdep.h>
40#include <asm/processor.h>
41#include <asm/siginfo.h>
42#include <asm/tlbflush.h>
43
44#include "traps.h"
45#include "../mm/fault.h"
46
47static const char *vec_names[] = {
48	[VEC_RESETSP]	= "RESET SP",
49	[VEC_RESETPC]	= "RESET PC",
50	[VEC_BUSERR]	= "BUS ERROR",
51	[VEC_ADDRERR]	= "ADDRESS ERROR",
52	[VEC_ILLEGAL]	= "ILLEGAL INSTRUCTION",
53	[VEC_ZERODIV]	= "ZERO DIVIDE",
54	[VEC_CHK]	= "CHK",
55	[VEC_TRAP]	= "TRAPcc",
56	[VEC_PRIV]	= "PRIVILEGE VIOLATION",
57	[VEC_TRACE]	= "TRACE",
58	[VEC_LINE10]	= "LINE 1010",
59	[VEC_LINE11]	= "LINE 1111",
60	[VEC_RESV12]	= "UNASSIGNED RESERVED 12",
61	[VEC_COPROC]	= "COPROCESSOR PROTOCOL VIOLATION",
62	[VEC_FORMAT]	= "FORMAT ERROR",
63	[VEC_UNINT]	= "UNINITIALIZED INTERRUPT",
64	[VEC_RESV16]	= "UNASSIGNED RESERVED 16",
65	[VEC_RESV17]	= "UNASSIGNED RESERVED 17",
66	[VEC_RESV18]	= "UNASSIGNED RESERVED 18",
67	[VEC_RESV19]	= "UNASSIGNED RESERVED 19",
68	[VEC_RESV20]	= "UNASSIGNED RESERVED 20",
69	[VEC_RESV21]	= "UNASSIGNED RESERVED 21",
70	[VEC_RESV22]	= "UNASSIGNED RESERVED 22",
71	[VEC_RESV23]	= "UNASSIGNED RESERVED 23",
72	[VEC_SPUR]	= "SPURIOUS INTERRUPT",
73	[VEC_INT1]	= "LEVEL 1 INT",
74	[VEC_INT2]	= "LEVEL 2 INT",
75	[VEC_INT3]	= "LEVEL 3 INT",
76	[VEC_INT4]	= "LEVEL 4 INT",
77	[VEC_INT5]	= "LEVEL 5 INT",
78	[VEC_INT6]	= "LEVEL 6 INT",
79	[VEC_INT7]	= "LEVEL 7 INT",
80	[VEC_SYS]	= "SYSCALL",
81	[VEC_TRAP1]	= "TRAP #1",
82	[VEC_TRAP2]	= "TRAP #2",
83	[VEC_TRAP3]	= "TRAP #3",
84	[VEC_TRAP4]	= "TRAP #4",
85	[VEC_TRAP5]	= "TRAP #5",
86	[VEC_TRAP6]	= "TRAP #6",
87	[VEC_TRAP7]	= "TRAP #7",
88	[VEC_TRAP8]	= "TRAP #8",
89	[VEC_TRAP9]	= "TRAP #9",
90	[VEC_TRAP10]	= "TRAP #10",
91	[VEC_TRAP11]	= "TRAP #11",
92	[VEC_TRAP12]	= "TRAP #12",
93	[VEC_TRAP13]	= "TRAP #13",
94	[VEC_TRAP14]	= "TRAP #14",
95	[VEC_TRAP15]	= "TRAP #15",
96	[VEC_FPBRUC]	= "FPCP BSUN",
97	[VEC_FPIR]	= "FPCP INEXACT",
98	[VEC_FPDIVZ]	= "FPCP DIV BY 0",
99	[VEC_FPUNDER]	= "FPCP UNDERFLOW",
100	[VEC_FPOE]	= "FPCP OPERAND ERROR",
101	[VEC_FPOVER]	= "FPCP OVERFLOW",
102	[VEC_FPNAN]	= "FPCP SNAN",
103	[VEC_FPUNSUP]	= "FPCP UNSUPPORTED OPERATION",
104	[VEC_MMUCFG]	= "MMU CONFIGURATION ERROR",
105	[VEC_MMUILL]	= "MMU ILLEGAL OPERATION ERROR",
106	[VEC_MMUACC]	= "MMU ACCESS LEVEL VIOLATION ERROR",
107	[VEC_RESV59]	= "UNASSIGNED RESERVED 59",
108	[VEC_UNIMPEA]	= "UNASSIGNED RESERVED 60",
109	[VEC_UNIMPII]	= "UNASSIGNED RESERVED 61",
110	[VEC_RESV62]	= "UNASSIGNED RESERVED 62",
111	[VEC_RESV63]	= "UNASSIGNED RESERVED 63",
112};
113
114static const char *space_names[] = {
115	[0]		= "Space 0",
116	[USER_DATA]	= "User Data",
117	[USER_PROGRAM]	= "User Program",
118#ifndef CONFIG_SUN3
119	[3]		= "Space 3",
120#else
121	[FC_CONTROL]	= "Control",
122#endif
123	[4]		= "Space 4",
124	[SUPER_DATA]	= "Super Data",
125	[SUPER_PROGRAM]	= "Super Program",
126	[CPU_SPACE]	= "CPU"
127};
128
129void die_if_kernel(char *,struct pt_regs *,int);
130asmlinkage void trap_c(struct frame *fp);
131
132#if defined (CONFIG_M68060)
133static inline void access_error060 (struct frame *fp)
134{
135	unsigned long fslw = fp->un.fmt4.pc; /* is really FSLW for access error */
136
137	pr_debug("fslw=%#lx, fa=%#lx\n", fslw, fp->un.fmt4.effaddr);
138
139	if (fslw & MMU060_BPE) {
140		/* branch prediction error -> clear branch cache */
141		__asm__ __volatile__ ("movec %/cacr,%/d0\n\t"
142				      "orl   #0x00400000,%/d0\n\t"
143				      "movec %/d0,%/cacr"
144				      : : : "d0" );
145		/* return if there's no other error */
146		if (!(fslw & MMU060_ERR_BITS) && !(fslw & MMU060_SEE))
147			return;
148	}
149
150	if (fslw & (MMU060_DESC_ERR | MMU060_WP | MMU060_SP)) {
151		unsigned long errorcode;
152		unsigned long addr = fp->un.fmt4.effaddr;
153
154		if (fslw & MMU060_MA)
155			addr = (addr + PAGE_SIZE - 1) & PAGE_MASK;
156
157		errorcode = 1;
158		if (fslw & MMU060_DESC_ERR) {
159			__flush_tlb040_one(addr);
160			errorcode = 0;
161		}
162		if (fslw & MMU060_W)
163			errorcode |= 2;
164		pr_debug("errorcode = %ld\n", errorcode);
165		do_page_fault(&fp->ptregs, addr, errorcode);
166	} else if (fslw & (MMU060_SEE)){
167		/* Software Emulation Error.
168		 * fault during mem_read/mem_write in ifpsp060/os.S
169		 */
170		send_fault_sig(&fp->ptregs);
171	} else if (!(fslw & (MMU060_RE|MMU060_WE)) ||
172		   send_fault_sig(&fp->ptregs) > 0) {
173		pr_err("pc=%#lx, fa=%#lx\n", fp->ptregs.pc,
174		       fp->un.fmt4.effaddr);
175		pr_err("68060 access error, fslw=%lx\n", fslw);
176		trap_c( fp );
177	}
178}
179#endif /* CONFIG_M68060 */
180
181#if defined (CONFIG_M68040)
182static inline unsigned long probe040(int iswrite, unsigned long addr, int wbs)
183{
184	unsigned long mmusr;
185
186	set_fc(wbs);
187
188	if (iswrite)
189		asm volatile (".chip 68040; ptestw (%0); .chip 68k" : : "a" (addr));
190	else
191		asm volatile (".chip 68040; ptestr (%0); .chip 68k" : : "a" (addr));
192
193	asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr));
194
195	set_fc(USER_DATA);
196
197	return mmusr;
198}
199
200static inline int do_040writeback1(unsigned short wbs, unsigned long wba,
201				   unsigned long wbd)
202{
203	int res = 0;
204
205	set_fc(wbs);
206
207	switch (wbs & WBSIZ_040) {
208	case BA_SIZE_BYTE:
209		res = put_user(wbd & 0xff, (char __user *)wba);
210		break;
211	case BA_SIZE_WORD:
212		res = put_user(wbd & 0xffff, (short __user *)wba);
213		break;
214	case BA_SIZE_LONG:
215		res = put_user(wbd, (int __user *)wba);
216		break;
217	}
218
219	set_fc(USER_DATA);
220
221	pr_debug("do_040writeback1, res=%d\n", res);
222
223	return res;
224}
225
226/* after an exception in a writeback the stack frame corresponding
227 * to that exception is discarded, set a few bits in the old frame
228 * to simulate what it should look like
229 */
230static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs)
231{
232	fp->un.fmt7.faddr = wba;
233	fp->un.fmt7.ssw = wbs & 0xff;
234	if (wba != current->thread.faddr)
235	    fp->un.fmt7.ssw |= MA_040;
236}
237
238static inline void do_040writebacks(struct frame *fp)
239{
240	int res = 0;
241#if 0
242	if (fp->un.fmt7.wb1s & WBV_040)
243		pr_err("access_error040: cannot handle 1st writeback. oops.\n");
244#endif
245
246	if ((fp->un.fmt7.wb2s & WBV_040) &&
247	    !(fp->un.fmt7.wb2s & WBTT_040)) {
248		res = do_040writeback1(fp->un.fmt7.wb2s, fp->un.fmt7.wb2a,
249				       fp->un.fmt7.wb2d);
250		if (res)
251			fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s);
252		else
253			fp->un.fmt7.wb2s = 0;
254	}
255
256	/* do the 2nd wb only if the first one was successful (except for a kernel wb) */
257	if (fp->un.fmt7.wb3s & WBV_040 && (!res || fp->un.fmt7.wb3s & 4)) {
258		res = do_040writeback1(fp->un.fmt7.wb3s, fp->un.fmt7.wb3a,
259				       fp->un.fmt7.wb3d);
260		if (res)
261		    {
262			fix_xframe040(fp, fp->un.fmt7.wb3a, fp->un.fmt7.wb3s);
263
264			fp->un.fmt7.wb2s = fp->un.fmt7.wb3s;
265			fp->un.fmt7.wb3s &= (~WBV_040);
266			fp->un.fmt7.wb2a = fp->un.fmt7.wb3a;
267			fp->un.fmt7.wb2d = fp->un.fmt7.wb3d;
268		    }
269		else
270			fp->un.fmt7.wb3s = 0;
271	}
272
273	if (res)
274		send_fault_sig(&fp->ptregs);
275}
276
277/*
278 * called from sigreturn(), must ensure userspace code didn't
279 * manipulate exception frame to circumvent protection, then complete
280 * pending writebacks
281 * we just clear TM2 to turn it into a userspace access
282 */
283asmlinkage void berr_040cleanup(struct frame *fp)
284{
285	fp->un.fmt7.wb2s &= ~4;
286	fp->un.fmt7.wb3s &= ~4;
287
288	do_040writebacks(fp);
289}
290
291static inline void access_error040(struct frame *fp)
292{
293	unsigned short ssw = fp->un.fmt7.ssw;
294	unsigned long mmusr;
295
296	pr_debug("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr);
297	pr_debug("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s,
298		fp->un.fmt7.wb2s, fp->un.fmt7.wb3s);
299	pr_debug("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n",
300		fp->un.fmt7.wb2a, fp->un.fmt7.wb3a,
301		fp->un.fmt7.wb2d, fp->un.fmt7.wb3d);
302
303	if (ssw & ATC_040) {
304		unsigned long addr = fp->un.fmt7.faddr;
305		unsigned long errorcode;
306
307		/*
308		 * The MMU status has to be determined AFTER the address
309		 * has been corrected if there was a misaligned access (MA).
310		 */
311		if (ssw & MA_040)
312			addr = (addr + 7) & -8;
313
314		/* MMU error, get the MMUSR info for this access */
315		mmusr = probe040(!(ssw & RW_040), addr, ssw);
316		pr_debug("mmusr = %lx\n", mmusr);
317		errorcode = 1;
318		if (!(mmusr & MMU_R_040)) {
319			/* clear the invalid atc entry */
320			__flush_tlb040_one(addr);
321			errorcode = 0;
322		}
323
324		/* despite what documentation seems to say, RMW
325		 * accesses have always both the LK and RW bits set */
326		if (!(ssw & RW_040) || (ssw & LK_040))
327			errorcode |= 2;
328
329		if (do_page_fault(&fp->ptregs, addr, errorcode)) {
330			pr_debug("do_page_fault() !=0\n");
331			if (user_mode(&fp->ptregs)){
332				/* delay writebacks after signal delivery */
333				pr_debug(".. was usermode - return\n");
334				return;
335			}
336			/* disable writeback into user space from kernel
337			 * (if do_page_fault didn't fix the mapping,
338                         * the writeback won't do good)
339			 */
340disable_wb:
341			pr_debug(".. disabling wb2\n");
342			if (fp->un.fmt7.wb2a == fp->un.fmt7.faddr)
343				fp->un.fmt7.wb2s &= ~WBV_040;
344			if (fp->un.fmt7.wb3a == fp->un.fmt7.faddr)
345				fp->un.fmt7.wb3s &= ~WBV_040;
346		}
347	} else {
348		/* In case of a bus error we either kill the process or expect
349		 * the kernel to catch the fault, which then is also responsible
350		 * for cleaning up the mess.
351		 */
352		current->thread.signo = SIGBUS;
353		current->thread.faddr = fp->un.fmt7.faddr;
354		if (send_fault_sig(&fp->ptregs) >= 0)
355			pr_err("68040 bus error (ssw=%x, faddr=%lx)\n", ssw,
356			       fp->un.fmt7.faddr);
357		goto disable_wb;
358	}
359
360	do_040writebacks(fp);
361}
362#endif /* CONFIG_M68040 */
363
364#if defined(CONFIG_SUN3)
365#include <asm/sun3mmu.h>
366
367#include "../sun3/sun3.h"
368
369/* sun3 version of bus_error030 */
370
371static inline void bus_error030 (struct frame *fp)
372{
373	unsigned char buserr_type = sun3_get_buserr ();
374	unsigned long addr, errorcode;
375	unsigned short ssw = fp->un.fmtb.ssw;
376	extern unsigned long _sun3_map_test_start, _sun3_map_test_end;
377
378	if (ssw & (FC | FB))
379		pr_debug("Instruction fault at %#010lx\n",
380			ssw & FC ?
381			fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
382			:
383			fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
384	if (ssw & DF)
385		pr_debug("Data %s fault at %#010lx in %s (pc=%#lx)\n",
386			ssw & RW ? "read" : "write",
387			fp->un.fmtb.daddr,
388			space_names[ssw & DFC], fp->ptregs.pc);
389
390	/*
391	 * Check if this page should be demand-mapped. This needs to go before
392	 * the testing for a bad kernel-space access (demand-mapping applies
393	 * to kernel accesses too).
394	 */
395
396	if ((ssw & DF)
397	    && (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) {
398		if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0))
399			return;
400	}
401
402	/* Check for kernel-space pagefault (BAD). */
403	if (fp->ptregs.sr & PS_S) {
404		/* kernel fault must be a data fault to user space */
405		if (! ((ssw & DF) && ((ssw & DFC) == USER_DATA))) {
406		     // try checking the kernel mappings before surrender
407		     if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 1))
408			  return;
409			/* instruction fault or kernel data fault! */
410			if (ssw & (FC | FB))
411				pr_err("Instruction fault at %#010lx\n",
412					fp->ptregs.pc);
413			if (ssw & DF) {
414				/* was this fault incurred testing bus mappings? */
415				if((fp->ptregs.pc >= (unsigned long)&_sun3_map_test_start) &&
416				   (fp->ptregs.pc <= (unsigned long)&_sun3_map_test_end)) {
417					send_fault_sig(&fp->ptregs);
418					return;
419				}
420
421				pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
422					ssw & RW ? "read" : "write",
423					fp->un.fmtb.daddr,
424					space_names[ssw & DFC], fp->ptregs.pc);
425			}
426			pr_err("BAD KERNEL BUSERR\n");
427
428			die_if_kernel("Oops", &fp->ptregs,0);
429			force_sig(SIGKILL);
430			return;
431		}
432	} else {
433		/* user fault */
434		if (!(ssw & (FC | FB)) && !(ssw & DF))
435			/* not an instruction fault or data fault! BAD */
436			panic ("USER BUSERR w/o instruction or data fault");
437	}
438
439
440	/* First handle the data fault, if any.  */
441	if (ssw & DF) {
442		addr = fp->un.fmtb.daddr;
443
444// errorcode bit 0:	0 -> no page		1 -> protection fault
445// errorcode bit 1:	0 -> read fault		1 -> write fault
446
447// (buserr_type & SUN3_BUSERR_PROTERR)	-> protection fault
448// (buserr_type & SUN3_BUSERR_INVALID)	-> invalid page fault
449
450		if (buserr_type & SUN3_BUSERR_PROTERR)
451			errorcode = 0x01;
452		else if (buserr_type & SUN3_BUSERR_INVALID)
453			errorcode = 0x00;
454		else {
455			pr_debug("*** unexpected busfault type=%#04x\n",
456				 buserr_type);
457			pr_debug("invalid %s access at %#lx from pc %#lx\n",
458				 !(ssw & RW) ? "write" : "read", addr,
459				 fp->ptregs.pc);
460			die_if_kernel ("Oops", &fp->ptregs, buserr_type);
461			force_sig (SIGBUS);
462			return;
463		}
464
465//todo: wtf is RM bit? --m
466		if (!(ssw & RW) || ssw & RM)
467			errorcode |= 0x02;
468
469		/* Handle page fault. */
470		do_page_fault (&fp->ptregs, addr, errorcode);
471
472		/* Retry the data fault now. */
473		return;
474	}
475
476	/* Now handle the instruction fault. */
477
478	/* Get the fault address. */
479	if (fp->ptregs.format == 0xA)
480		addr = fp->ptregs.pc + 4;
481	else
482		addr = fp->un.fmtb.baddr;
483	if (ssw & FC)
484		addr -= 2;
485
486	if (buserr_type & SUN3_BUSERR_INVALID) {
487		if (!mmu_emu_handle_fault(addr, 1, 0))
488			do_page_fault (&fp->ptregs, addr, 0);
489	} else {
490		pr_debug("protection fault on insn access (segv).\n");
491		force_sig (SIGSEGV);
492	}
493}
494#else
495#if defined(CPU_M68020_OR_M68030)
496static inline void bus_error030 (struct frame *fp)
497{
498	volatile unsigned short temp;
499	unsigned short mmusr;
500	unsigned long addr, errorcode;
501	unsigned short ssw = fp->un.fmtb.ssw;
502#ifdef DEBUG
503	unsigned long desc;
504#endif
505
506	pr_debug("pid = %x  ", current->pid);
507	pr_debug("SSW=%#06x  ", ssw);
508
509	if (ssw & (FC | FB))
510		pr_debug("Instruction fault at %#010lx\n",
511			ssw & FC ?
512			fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
513			:
514			fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
515	if (ssw & DF)
516		pr_debug("Data %s fault at %#010lx in %s (pc=%#lx)\n",
517			ssw & RW ? "read" : "write",
518			fp->un.fmtb.daddr,
519			space_names[ssw & DFC], fp->ptregs.pc);
520
521	/* ++andreas: If a data fault and an instruction fault happen
522	   at the same time map in both pages.  */
523
524	/* First handle the data fault, if any.  */
525	if (ssw & DF) {
526		addr = fp->un.fmtb.daddr;
527
528#ifdef DEBUG
529		asm volatile ("ptestr %3,%2@,#7,%0\n\t"
530			      "pmove %%psr,%1"
531			      : "=a&" (desc), "=m" (temp)
532			      : "a" (addr), "d" (ssw));
533		pr_debug("mmusr is %#x for addr %#lx in task %p\n",
534			 temp, addr, current);
535		pr_debug("descriptor address is 0x%p, contents %#lx\n",
536			 __va(desc), *(unsigned long *)__va(desc));
537#else
538		asm volatile ("ptestr %2,%1@,#7\n\t"
539			      "pmove %%psr,%0"
540			      : "=m" (temp) : "a" (addr), "d" (ssw));
541#endif
542		mmusr = temp;
543		errorcode = (mmusr & MMU_I) ? 0 : 1;
544		if (!(ssw & RW) || (ssw & RM))
545			errorcode |= 2;
546
547		if (mmusr & (MMU_I | MMU_WP)) {
548			/* We might have an exception table for this PC */
549			if (ssw & 4 && !search_exception_tables(fp->ptregs.pc)) {
550				pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
551				       ssw & RW ? "read" : "write",
552				       fp->un.fmtb.daddr,
553				       space_names[ssw & DFC], fp->ptregs.pc);
554				goto buserr;
555			}
556			/* Don't try to do anything further if an exception was
557			   handled. */
558			if (do_page_fault (&fp->ptregs, addr, errorcode) < 0)
559				return;
560		} else if (!(mmusr & MMU_I)) {
561			/* probably a 020 cas fault */
562			if (!(ssw & RM) && send_fault_sig(&fp->ptregs) > 0)
563				pr_err("unexpected bus error (%#x,%#x)\n", ssw,
564				       mmusr);
565		} else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
566			pr_err("invalid %s access at %#lx from pc %#lx\n",
567			       !(ssw & RW) ? "write" : "read", addr,
568			       fp->ptregs.pc);
569			die_if_kernel("Oops",&fp->ptregs,mmusr);
570			force_sig(SIGSEGV);
571			return;
572		} else {
573#if 0
574			static volatile long tlong;
575#endif
576
577			pr_err("weird %s access at %#lx from pc %#lx (ssw is %#x)\n",
578			       !(ssw & RW) ? "write" : "read", addr,
579			       fp->ptregs.pc, ssw);
580			asm volatile ("ptestr #1,%1@,#0\n\t"
581				      "pmove %%psr,%0"
582				      : "=m" (temp)
583				      : "a" (addr));
584			mmusr = temp;
585
586			pr_err("level 0 mmusr is %#x\n", mmusr);
587#if 0
588			asm volatile ("pmove %%tt0,%0"
589				      : "=m" (tlong));
590			pr_debug("tt0 is %#lx, ", tlong);
591			asm volatile ("pmove %%tt1,%0"
592				      : "=m" (tlong));
593			pr_debug("tt1 is %#lx\n", tlong);
594#endif
595			pr_debug("Unknown SIGSEGV - 1\n");
596			die_if_kernel("Oops",&fp->ptregs,mmusr);
597			force_sig(SIGSEGV);
598			return;
599		}
600
601		/* setup an ATC entry for the access about to be retried */
602		if (!(ssw & RW) || (ssw & RM))
603			asm volatile ("ploadw %1,%0@" : /* no outputs */
604				      : "a" (addr), "d" (ssw));
605		else
606			asm volatile ("ploadr %1,%0@" : /* no outputs */
607				      : "a" (addr), "d" (ssw));
608	}
609
610	/* Now handle the instruction fault. */
611
612	if (!(ssw & (FC|FB)))
613		return;
614
615	if (fp->ptregs.sr & PS_S) {
616		pr_err("Instruction fault at %#010lx\n", fp->ptregs.pc);
617	buserr:
618		pr_err("BAD KERNEL BUSERR\n");
619		die_if_kernel("Oops",&fp->ptregs,0);
620		force_sig(SIGKILL);
621		return;
622	}
623
624	/* get the fault address */
625	if (fp->ptregs.format == 10)
626		addr = fp->ptregs.pc + 4;
627	else
628		addr = fp->un.fmtb.baddr;
629	if (ssw & FC)
630		addr -= 2;
631
632	if ((ssw & DF) && ((addr ^ fp->un.fmtb.daddr) & PAGE_MASK) == 0)
633		/* Insn fault on same page as data fault.  But we
634		   should still create the ATC entry.  */
635		goto create_atc_entry;
636
637#ifdef DEBUG
638	asm volatile ("ptestr #1,%2@,#7,%0\n\t"
639		      "pmove %%psr,%1"
640		      : "=a&" (desc), "=m" (temp)
641		      : "a" (addr));
642	pr_debug("mmusr is %#x for addr %#lx in task %p\n",
643		temp, addr, current);
644	pr_debug("descriptor address is 0x%p, contents %#lx\n",
645		__va(desc), *(unsigned long *)__va(desc));
646#else
647	asm volatile ("ptestr #1,%1@,#7\n\t"
648		      "pmove %%psr,%0"
649		      : "=m" (temp) : "a" (addr));
650#endif
651	mmusr = temp;
652	if (mmusr & MMU_I)
653		do_page_fault (&fp->ptregs, addr, 0);
654	else if (mmusr & (MMU_B|MMU_L|MMU_S)) {
655		pr_err("invalid insn access at %#lx from pc %#lx\n",
656			addr, fp->ptregs.pc);
657		pr_debug("Unknown SIGSEGV - 2\n");
658		die_if_kernel("Oops",&fp->ptregs,mmusr);
659		force_sig(SIGSEGV);
660		return;
661	}
662
663create_atc_entry:
664	/* setup an ATC entry for the access about to be retried */
665	asm volatile ("ploadr #2,%0@" : /* no outputs */
666		      : "a" (addr));
667}
668#endif /* CPU_M68020_OR_M68030 */
669#endif /* !CONFIG_SUN3 */
670
671#if defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
672#include <asm/mcfmmu.h>
673
674/*
675 *	The following table converts the FS encoding of a ColdFire
676 *	exception stack frame into the error_code value needed by
677 *	do_fault.
678*/
679static const unsigned char fs_err_code[] = {
680	0,  /* 0000 */
681	0,  /* 0001 */
682	0,  /* 0010 */
683	0,  /* 0011 */
684	1,  /* 0100 */
685	0,  /* 0101 */
686	0,  /* 0110 */
687	0,  /* 0111 */
688	2,  /* 1000 */
689	3,  /* 1001 */
690	2,  /* 1010 */
691	0,  /* 1011 */
692	1,  /* 1100 */
693	1,  /* 1101 */
694	0,  /* 1110 */
695	0   /* 1111 */
696};
697
698static inline void access_errorcf(unsigned int fs, struct frame *fp)
699{
700	unsigned long mmusr, addr;
701	unsigned int err_code;
702	int need_page_fault;
703
704	mmusr = mmu_read(MMUSR);
705	addr = mmu_read(MMUAR);
706
707	/*
708	 * error_code:
709	 *	bit 0 == 0 means no page found, 1 means protection fault
710	 *	bit 1 == 0 means read, 1 means write
711	 */
712	switch (fs) {
713	case  5:  /* 0101 TLB opword X miss */
714		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0);
715		addr = fp->ptregs.pc;
716		break;
717	case  6:  /* 0110 TLB extension word X miss */
718		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1);
719		addr = fp->ptregs.pc + sizeof(long);
720		break;
721	case 10:  /* 1010 TLB W miss */
722		need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0);
723		break;
724	case 14: /* 1110 TLB R miss */
725		need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0);
726		break;
727	default:
728		/* 0000 Normal  */
729		/* 0001 Reserved */
730		/* 0010 Interrupt during debug service routine */
731		/* 0011 Reserved */
732		/* 0100 X Protection */
733		/* 0111 IFP in emulator mode */
734		/* 1000 W Protection*/
735		/* 1001 Write error*/
736		/* 1011 Reserved*/
737		/* 1100 R Protection*/
738		/* 1101 R Protection*/
739		/* 1111 OEP in emulator mode*/
740		need_page_fault = 1;
741		break;
742	}
743
744	if (need_page_fault) {
745		err_code = fs_err_code[fs];
746		if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */
747			err_code |= 2; /* bit1 - write, bit0 - protection */
748		do_page_fault(&fp->ptregs, addr, err_code);
749	}
750}
751#endif /* CONFIG_COLDFIRE CONFIG_MMU */
752
753asmlinkage void buserr_c(struct frame *fp)
754{
755	/* Only set esp0 if coming from user mode */
756	if (user_mode(&fp->ptregs))
757		current->thread.esp0 = (unsigned long) fp;
758
759	pr_debug("*** Bus Error *** Format is %x\n", fp->ptregs.format);
760
761#if defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
762	if (CPU_IS_COLDFIRE) {
763		unsigned int fs;
764		fs = (fp->ptregs.vector & 0x3) |
765			((fp->ptregs.vector & 0xc00) >> 8);
766		switch (fs) {
767		case 0x5:
768		case 0x6:
769		case 0x7:
770		case 0x9:
771		case 0xa:
772		case 0xd:
773		case 0xe:
774		case 0xf:
775			access_errorcf(fs, fp);
776			return;
777		default:
778			break;
779		}
780	}
781#endif /* CONFIG_COLDFIRE && CONFIG_MMU */
782
783	switch (fp->ptregs.format) {
784#if defined (CONFIG_M68060)
785	case 4:				/* 68060 access error */
786	  access_error060 (fp);
787	  break;
788#endif
789#if defined (CONFIG_M68040)
790	case 0x7:			/* 68040 access error */
791	  access_error040 (fp);
792	  break;
793#endif
794#if defined (CPU_M68020_OR_M68030)
795	case 0xa:
796	case 0xb:
797	  bus_error030 (fp);
798	  break;
799#endif
800	default:
801	  die_if_kernel("bad frame format",&fp->ptregs,0);
802	  pr_debug("Unknown SIGSEGV - 4\n");
803	  force_sig(SIGSEGV);
804	}
805}
806
807
808static int kstack_depth_to_print = 48;
809
810static void show_trace(unsigned long *stack, const char *loglvl)
811{
812	unsigned long *endstack;
813	unsigned long addr;
814	int i;
815
816	printk("%sCall Trace:", loglvl);
817	addr = (unsigned long)stack + THREAD_SIZE - 1;
818	endstack = (unsigned long *)(addr & -THREAD_SIZE);
819	i = 0;
820	while (stack + 1 <= endstack) {
821		addr = *stack++;
822		/*
823		 * If the address is either in the text segment of the
824		 * kernel, or in the region which contains vmalloc'ed
825		 * memory, it *may* be the address of a calling
826		 * routine; if so, print it so that someone tracing
827		 * down the cause of the crash will be able to figure
828		 * out the call path that was taken.
829		 */
830		if (__kernel_text_address(addr)) {
831#ifndef CONFIG_KALLSYMS
832			if (i % 5 == 0)
833				pr_cont("\n       ");
834#endif
835			pr_cont(" [<%08lx>] %pS\n", addr, (void *)addr);
836			i++;
837		}
838	}
839	pr_cont("\n");
840}
841
842void show_registers(struct pt_regs *regs)
843{
844	struct frame *fp = (struct frame *)regs;
845	u16 c, *cp;
846	unsigned long addr;
847	int i;
848
849	print_modules();
850	pr_info("PC: [<%08lx>] %pS\n", regs->pc, (void *)regs->pc);
851	pr_info("SR: %04x  SP: %p  a2: %08lx\n", regs->sr, regs, regs->a2);
852	pr_info("d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
853		regs->d0, regs->d1, regs->d2, regs->d3);
854	pr_info("d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
855		regs->d4, regs->d5, regs->a0, regs->a1);
856
857	pr_info("Process %s (pid: %d, task=%p)\n",
858		current->comm, task_pid_nr(current), current);
859	addr = (unsigned long)&fp->un;
860	pr_info("Frame format=%X ", regs->format);
861	switch (regs->format) {
862	case 0x2:
863		pr_cont("instr addr=%08lx\n", fp->un.fmt2.iaddr);
864		addr += sizeof(fp->un.fmt2);
865		break;
866	case 0x3:
867		pr_cont("eff addr=%08lx\n", fp->un.fmt3.effaddr);
868		addr += sizeof(fp->un.fmt3);
869		break;
870	case 0x4:
871		if (CPU_IS_060)
872			pr_cont("fault addr=%08lx fslw=%08lx\n",
873				fp->un.fmt4.effaddr, fp->un.fmt4.pc);
874		else
875			pr_cont("eff addr=%08lx pc=%08lx\n",
876				fp->un.fmt4.effaddr, fp->un.fmt4.pc);
877		addr += sizeof(fp->un.fmt4);
878		break;
879	case 0x7:
880		pr_cont("eff addr=%08lx ssw=%04x faddr=%08lx\n",
881			fp->un.fmt7.effaddr, fp->un.fmt7.ssw, fp->un.fmt7.faddr);
882		pr_info("wb 1 stat/addr/data: %04x %08lx %08lx\n",
883			fp->un.fmt7.wb1s, fp->un.fmt7.wb1a, fp->un.fmt7.wb1dpd0);
884		pr_info("wb 2 stat/addr/data: %04x %08lx %08lx\n",
885			fp->un.fmt7.wb2s, fp->un.fmt7.wb2a, fp->un.fmt7.wb2d);
886		pr_info("wb 3 stat/addr/data: %04x %08lx %08lx\n",
887			fp->un.fmt7.wb3s, fp->un.fmt7.wb3a, fp->un.fmt7.wb3d);
888		pr_info("push data: %08lx %08lx %08lx %08lx\n",
889			fp->un.fmt7.wb1dpd0, fp->un.fmt7.pd1, fp->un.fmt7.pd2,
890			fp->un.fmt7.pd3);
891		addr += sizeof(fp->un.fmt7);
892		break;
893	case 0x9:
894		pr_cont("instr addr=%08lx\n", fp->un.fmt9.iaddr);
895		addr += sizeof(fp->un.fmt9);
896		break;
897	case 0xa:
898		pr_cont("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
899			fp->un.fmta.ssw, fp->un.fmta.isc, fp->un.fmta.isb,
900			fp->un.fmta.daddr, fp->un.fmta.dobuf);
901		addr += sizeof(fp->un.fmta);
902		break;
903	case 0xb:
904		pr_cont("ssw=%04x isc=%04x isb=%04x daddr=%08lx dobuf=%08lx\n",
905			fp->un.fmtb.ssw, fp->un.fmtb.isc, fp->un.fmtb.isb,
906			fp->un.fmtb.daddr, fp->un.fmtb.dobuf);
907		pr_info("baddr=%08lx dibuf=%08lx ver=%x\n",
908			fp->un.fmtb.baddr, fp->un.fmtb.dibuf, fp->un.fmtb.ver);
909		addr += sizeof(fp->un.fmtb);
910		break;
911	default:
912		pr_cont("\n");
913	}
914	show_stack(NULL, (unsigned long *)addr, KERN_INFO);
915
916	pr_info("Code:");
917	cp = (u16 *)regs->pc;
918	for (i = -8; i < 16; i++) {
919		if (get_kernel_nofault(c, cp + i) && i >= 0) {
920			pr_cont(" Bad PC value.");
921			break;
922		}
923		if (i)
924			pr_cont(" %04x", c);
925		else
926			pr_cont(" <%04x>", c);
927	}
928	pr_cont("\n");
929}
930
931void show_stack(struct task_struct *task, unsigned long *stack,
932		const char *loglvl)
933{
934	unsigned long *p;
935	unsigned long *endstack;
936	int i;
937
938	if (!stack) {
939		if (task)
940			stack = (unsigned long *)task->thread.esp0;
941		else
942			stack = (unsigned long *)&stack;
943	}
944	endstack = (unsigned long *)(((unsigned long)stack + THREAD_SIZE - 1) & -THREAD_SIZE);
945
946	printk("%sStack from %08lx:", loglvl, (unsigned long)stack);
947	p = stack;
948	for (i = 0; i < kstack_depth_to_print; i++) {
949		if (p + 1 > endstack)
950			break;
951		if (i % 8 == 0)
952			pr_cont("\n       ");
953		pr_cont(" %08lx", *p++);
954	}
955	pr_cont("\n");
956	show_trace(stack, loglvl);
957}
958
959/*
960 * The vector number returned in the frame pointer may also contain
961 * the "fs" (Fault Status) bits on ColdFire. These are in the bottom
962 * 2 bits, and upper 2 bits. So we need to mask out the real vector
963 * number before using it in comparisons. You don't need to do this on
964 * real 68k parts, but it won't hurt either.
965 */
966
967static void bad_super_trap(struct frame *fp)
968{
969	int vector = (fp->ptregs.vector >> 2) & 0xff;
970
971	console_verbose();
972	if (vector < ARRAY_SIZE(vec_names))
973		pr_err("*** %s ***   FORMAT=%X\n",
974			vec_names[vector],
975			fp->ptregs.format);
976	else
977		pr_err("*** Exception %d ***   FORMAT=%X\n",
978			vector, fp->ptregs.format);
979	if (vector == VEC_ADDRERR && CPU_IS_020_OR_030) {
980		unsigned short ssw = fp->un.fmtb.ssw;
981
982		pr_err("SSW=%#06x  ", ssw);
983
984		if (ssw & RC)
985			pr_err("Pipe stage C instruction fault at %#010lx\n",
986				(fp->ptregs.format) == 0xA ?
987				fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2);
988		if (ssw & RB)
989			pr_err("Pipe stage B instruction fault at %#010lx\n",
990				(fp->ptregs.format) == 0xA ?
991				fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
992		if (ssw & DF)
993			pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n",
994				ssw & RW ? "read" : "write",
995				fp->un.fmtb.daddr, space_names[ssw & DFC],
996				fp->ptregs.pc);
997	}
998	pr_err("Current process id is %d\n", task_pid_nr(current));
999	die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
1000}
1001
1002asmlinkage void trap_c(struct frame *fp)
1003{
1004	int sig, si_code;
1005	void __user *addr;
1006	int vector = (fp->ptregs.vector >> 2) & 0xff;
1007
1008	if (fp->ptregs.sr & PS_S) {
1009		if (vector == VEC_TRACE) {
1010			/* traced a trapping instruction on a 68020/30,
1011			 * real exception will be executed afterwards.
1012			 */
1013			return;
1014		}
1015#ifdef CONFIG_MMU
1016		if (fixup_exception(&fp->ptregs))
1017			return;
1018#endif
1019		bad_super_trap(fp);
1020		return;
1021	}
1022
1023	/* send the appropriate signal to the user program */
1024	switch (vector) {
1025	    case VEC_ADDRERR:
1026		si_code = BUS_ADRALN;
1027		sig = SIGBUS;
1028		break;
1029	    case VEC_ILLEGAL:
1030	    case VEC_LINE10:
1031	    case VEC_LINE11:
1032		si_code = ILL_ILLOPC;
1033		sig = SIGILL;
1034		break;
1035	    case VEC_PRIV:
1036		si_code = ILL_PRVOPC;
1037		sig = SIGILL;
1038		break;
1039	    case VEC_COPROC:
1040		si_code = ILL_COPROC;
1041		sig = SIGILL;
1042		break;
1043	    case VEC_TRAP1:
1044	    case VEC_TRAP2:
1045	    case VEC_TRAP3:
1046	    case VEC_TRAP4:
1047	    case VEC_TRAP5:
1048	    case VEC_TRAP6:
1049	    case VEC_TRAP7:
1050	    case VEC_TRAP8:
1051	    case VEC_TRAP9:
1052	    case VEC_TRAP10:
1053	    case VEC_TRAP11:
1054	    case VEC_TRAP12:
1055	    case VEC_TRAP13:
1056	    case VEC_TRAP14:
1057		si_code = ILL_ILLTRP;
1058		sig = SIGILL;
1059		break;
1060	    case VEC_FPBRUC:
1061	    case VEC_FPOE:
1062	    case VEC_FPNAN:
1063		si_code = FPE_FLTINV;
1064		sig = SIGFPE;
1065		break;
1066	    case VEC_FPIR:
1067		si_code = FPE_FLTRES;
1068		sig = SIGFPE;
1069		break;
1070	    case VEC_FPDIVZ:
1071		si_code = FPE_FLTDIV;
1072		sig = SIGFPE;
1073		break;
1074	    case VEC_FPUNDER:
1075		si_code = FPE_FLTUND;
1076		sig = SIGFPE;
1077		break;
1078	    case VEC_FPOVER:
1079		si_code = FPE_FLTOVF;
1080		sig = SIGFPE;
1081		break;
1082	    case VEC_ZERODIV:
1083		si_code = FPE_INTDIV;
1084		sig = SIGFPE;
1085		break;
1086	    case VEC_CHK:
1087	    case VEC_TRAP:
1088		si_code = FPE_INTOVF;
1089		sig = SIGFPE;
1090		break;
1091	    case VEC_TRACE:		/* ptrace single step */
1092		si_code = TRAP_TRACE;
1093		sig = SIGTRAP;
1094		break;
1095	    case VEC_TRAP15:		/* breakpoint */
1096		si_code = TRAP_BRKPT;
1097		sig = SIGTRAP;
1098		break;
1099	    default:
1100		si_code = ILL_ILLOPC;
1101		sig = SIGILL;
1102		break;
1103	}
1104	switch (fp->ptregs.format) {
1105	    default:
1106		addr = (void __user *) fp->ptregs.pc;
1107		break;
1108	    case 2:
1109		addr = (void __user *) fp->un.fmt2.iaddr;
1110		break;
1111	    case 7:
1112		addr = (void __user *) fp->un.fmt7.effaddr;
1113		break;
1114	    case 9:
1115		addr = (void __user *) fp->un.fmt9.iaddr;
1116		break;
1117	    case 10:
1118		addr = (void __user *) fp->un.fmta.daddr;
1119		break;
1120	    case 11:
1121		addr = (void __user*) fp->un.fmtb.daddr;
1122		break;
1123	}
1124	force_sig_fault(sig, si_code, addr);
1125}
1126
1127void die_if_kernel (char *str, struct pt_regs *fp, int nr)
1128{
1129	if (!(fp->sr & PS_S))
1130		return;
1131
1132	console_verbose();
1133	pr_crit("%s: %08x\n", str, nr);
1134	show_registers(fp);
1135	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
1136	make_task_dead(SIGSEGV);
1137}
1138
1139asmlinkage void set_esp0(unsigned long ssp)
1140{
1141	current->thread.esp0 = ssp;
1142}
1143
1144/*
1145 * This function is called if an error occur while accessing
1146 * user-space from the fpsp040 code.
1147 */
1148asmlinkage void fpsp040_die(void)
1149{
1150	force_exit_sig(SIGSEGV);
1151}
1152
1153#ifdef CONFIG_M68KFPU_EMU
1154asmlinkage void fpemu_signal(int signal, int code, void *addr)
1155{
1156	force_sig_fault(signal, code, addr);
1157}
1158#endif
1159