1/* SPDX-License-Identifier: GPL-2.0 */
2/****************************************************************************/
3
4/*
5 *	mcfintc.h -- support definitions for the simple ColdFire
6 *		     Interrupt Controller
7 *
8 * 	(C) Copyright 2009,  Greg Ungerer <gerg@uclinux.org>
9 */
10
11/****************************************************************************/
12#ifndef	mcfintc_h
13#define	mcfintc_h
14/****************************************************************************/
15
16/*
17 * Most of the older ColdFire parts use the same simple interrupt
18 * controller. This is currently used on the 5206, 5206e, 5249, 5307
19 * and 5407 parts.
20 *
21 * The builtin peripherals are masked through dedicated bits in the
22 * Interrupt Mask register (IMR) - and this is not indexed (or in any way
23 * related to) the actual interrupt number they use. So knowing the IRQ
24 * number doesn't explicitly map to a certain internal device for
25 * interrupt control purposes.
26 */
27
28/*
29 * Bit definitions for the ICR family of registers.
30 */
31#define	MCFSIM_ICR_AUTOVEC	0x80		/* Auto-vectored intr */
32#define	MCFSIM_ICR_LEVEL0	0x00		/* Level 0 intr */
33#define	MCFSIM_ICR_LEVEL1	0x04		/* Level 1 intr */
34#define	MCFSIM_ICR_LEVEL2	0x08		/* Level 2 intr */
35#define	MCFSIM_ICR_LEVEL3	0x0c		/* Level 3 intr */
36#define	MCFSIM_ICR_LEVEL4	0x10		/* Level 4 intr */
37#define	MCFSIM_ICR_LEVEL5	0x14		/* Level 5 intr */
38#define	MCFSIM_ICR_LEVEL6	0x18		/* Level 6 intr */
39#define	MCFSIM_ICR_LEVEL7	0x1c		/* Level 7 intr */
40
41#define	MCFSIM_ICR_PRI0		0x00		/* Priority 0 intr */
42#define	MCFSIM_ICR_PRI1		0x01		/* Priority 1 intr */
43#define	MCFSIM_ICR_PRI2		0x02		/* Priority 2 intr */
44#define	MCFSIM_ICR_PRI3		0x03		/* Priority 3 intr */
45
46/*
47 * IMR bit position definitions. Not all ColdFire parts with this interrupt
48 * controller actually support all of these interrupt sources. But the bit
49 * numbers are the same in all cores.
50 */
51#define	MCFINTC_EINT1		1		/* External int #1 */
52#define	MCFINTC_EINT2		2		/* External int #2 */
53#define	MCFINTC_EINT3		3		/* External int #3 */
54#define	MCFINTC_EINT4		4		/* External int #4 */
55#define	MCFINTC_EINT5		5		/* External int #5 */
56#define	MCFINTC_EINT6		6		/* External int #6 */
57#define	MCFINTC_EINT7		7		/* External int #7 */
58#define	MCFINTC_SWT		8		/* Software Watchdog */
59#define	MCFINTC_TIMER1		9
60#define	MCFINTC_TIMER2		10
61#define	MCFINTC_I2C		11		/* I2C / MBUS */
62#define	MCFINTC_UART0		12
63#define	MCFINTC_UART1		13
64#define	MCFINTC_DMA0		14
65#define	MCFINTC_DMA1		15
66#define	MCFINTC_DMA2		16
67#define	MCFINTC_DMA3		17
68#define	MCFINTC_QSPI		18
69
70#ifndef __ASSEMBLER__
71
72/*
73 * There is no one-is-one correspondance between the interrupt number (irq)
74 * and the bit fields on the mask register. So we create a per-cpu type
75 * mapping of irq to mask bit. The CPU platform code needs to register
76 * its supported irq's at init time, using this function.
77 */
78extern unsigned char mcf_irq2imr[];
79static inline void mcf_mapirq2imr(int irq, int imr)
80{
81	mcf_irq2imr[irq] = imr;
82}
83
84void mcf_autovector(int irq);
85void mcf_setimr(int index);
86void mcf_clrimr(int index);
87#endif
88
89/****************************************************************************/
90#endif	/* mcfintc_h */
91