1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *  arch/m68k/bvme6000/config.c
4 *
5 *  Copyright (C) 1997 Richard Hirst [richard@sleepie.demon.co.uk]
6 *
7 * Based on:
8 *
9 *  linux/amiga/config.c
10 *
11 *  Copyright (C) 1993 Hamish Macdonald
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/tty.h>
18#include <linux/clocksource.h>
19#include <linux/console.h>
20#include <linux/linkage.h>
21#include <linux/init.h>
22#include <linux/major.h>
23#include <linux/rtc.h>
24#include <linux/interrupt.h>
25#include <linux/bcd.h>
26
27#include <asm/bootinfo.h>
28#include <asm/bootinfo-vme.h>
29#include <asm/byteorder.h>
30#include <asm/setup.h>
31#include <asm/irq.h>
32#include <asm/traps.h>
33#include <asm/machdep.h>
34#include <asm/bvme6000hw.h>
35#include <asm/config.h>
36
37static void bvme6000_get_model(char *model);
38extern void bvme6000_sched_init(void);
39extern int bvme6000_hwclk (int, struct rtc_time *);
40extern void bvme6000_reset (void);
41void bvme6000_set_vectors (void);
42
43
44int __init bvme6000_parse_bootinfo(const struct bi_record *bi)
45{
46	if (be16_to_cpu(bi->tag) == BI_VME_TYPE)
47		return 0;
48	else
49		return 1;
50}
51
52void bvme6000_reset(void)
53{
54	volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
55
56	pr_info("\r\n\nCalled bvme6000_reset\r\n"
57		"\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r");
58	/* The string of returns is to delay the reset until the whole
59	 * message is output. */
60	/* Enable the watchdog, via PIT port C bit 4 */
61
62	pit->pcddr	|= 0x10;	/* WDOG enable */
63
64	while(1)
65		;
66}
67
68static void bvme6000_get_model(char *model)
69{
70    sprintf(model, "BVME%d000", m68k_cputype == CPU_68060 ? 6 : 4);
71}
72
73/*
74 * This function is called during kernel startup to initialize
75 * the bvme6000 IRQ handling routines.
76 */
77static void __init bvme6000_init_IRQ(void)
78{
79	m68k_setup_user_interrupt(VEC_USER, 192);
80}
81
82void __init config_bvme6000(void)
83{
84    volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
85
86    /* Board type is only set by newer versions of vmelilo/tftplilo */
87    if (!vme_brdtype) {
88	if (m68k_cputype == CPU_68060)
89	    vme_brdtype = VME_TYPE_BVME6000;
90	else
91	    vme_brdtype = VME_TYPE_BVME4000;
92    }
93#if 0
94    /* Call bvme6000_set_vectors() so ABORT will work, along with BVMBug
95     * debugger.  Note trap_init() will splat the abort vector, but
96     * bvme6000_init_IRQ() will put it back again.  Hopefully. */
97
98    bvme6000_set_vectors();
99#endif
100
101    mach_sched_init      = bvme6000_sched_init;
102    mach_init_IRQ        = bvme6000_init_IRQ;
103    mach_hwclk           = bvme6000_hwclk;
104    mach_reset		 = bvme6000_reset;
105    mach_get_model       = bvme6000_get_model;
106
107    pr_info("Board is %sconfigured as a System Controller\n",
108	    *config_reg_ptr & BVME_CONFIG_SW1 ? "" : "not ");
109
110    /* Now do the PIT configuration */
111
112    pit->pgcr	= 0x00;	/* Unidirectional 8 bit, no handshake for now */
113    pit->psrr	= 0x18;	/* PIACK and PIRQ functions enabled */
114    pit->pacr	= 0x00;	/* Sub Mode 00, H2 i/p, no DMA */
115    pit->padr	= 0x00;	/* Just to be tidy! */
116    pit->paddr	= 0x00;	/* All inputs for now (safest) */
117    pit->pbcr	= 0x80;	/* Sub Mode 1x, H4 i/p, no DMA */
118    pit->pbdr	= 0xbc | (*config_reg_ptr & BVME_CONFIG_SW1 ? 0 : 0x40);
119			/* PRI, SYSCON?, Level3, SCC clks from xtal */
120    pit->pbddr	= 0xf3;	/* Mostly outputs */
121    pit->pcdr	= 0x01;	/* PA transceiver disabled */
122    pit->pcddr	= 0x03;	/* WDOG disable */
123
124    /* Disable snooping for Ethernet and VME accesses */
125
126    bvme_acr_addrctl = 0;
127}
128
129
130static irqreturn_t bvme6000_abort_int(int irq, void *dev_id)
131{
132        unsigned long *new = (unsigned long *)vectors;
133        unsigned long *old = (unsigned long *)0xf8000000;
134
135        /* Wait for button release */
136        while (*(volatile unsigned char *)BVME_LOCAL_IRQ_STAT & BVME_ABORT_STATUS)
137                ;
138
139        *(new+4) = *(old+4);            /* Illegal instruction */
140        *(new+9) = *(old+9);            /* Trace */
141        *(new+47) = *(old+47);          /* Trap #15 */
142        *(new+0x1f) = *(old+0x1f);      /* ABORT switch */
143	return IRQ_HANDLED;
144}
145
146static u64 bvme6000_read_clk(struct clocksource *cs);
147
148static struct clocksource bvme6000_clk = {
149	.name   = "rtc",
150	.rating = 250,
151	.read   = bvme6000_read_clk,
152	.mask   = CLOCKSOURCE_MASK(32),
153	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
154};
155
156static u32 clk_total, clk_offset;
157
158#define RTC_TIMER_CLOCK_FREQ 8000000
159#define RTC_TIMER_CYCLES     (RTC_TIMER_CLOCK_FREQ / HZ)
160#define RTC_TIMER_COUNT      ((RTC_TIMER_CYCLES / 2) - 1)
161
162static irqreturn_t bvme6000_timer_int (int irq, void *dev_id)
163{
164    unsigned long flags;
165    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
166    unsigned char msr;
167
168    local_irq_save(flags);
169    msr = rtc->msr & 0xc0;
170    rtc->msr = msr | 0x20;		/* Ack the interrupt */
171    clk_total += RTC_TIMER_CYCLES;
172    clk_offset = 0;
173    legacy_timer_tick(1);
174    local_irq_restore(flags);
175
176    return IRQ_HANDLED;
177}
178
179/*
180 * Set up the RTC timer 1 to mode 2, so T1 output toggles every 5ms
181 * (40000 x 125ns).  It will interrupt every 10ms, when T1 goes low.
182 * So, when reading the elapsed time, you should read timer1,
183 * subtract it from 39999, and then add 40000 if T1 is high.
184 * That gives you the number of 125ns ticks in to the 10ms period,
185 * so divide by 8 to get the microsecond result.
186 */
187
188void bvme6000_sched_init (void)
189{
190    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
191    unsigned char msr = rtc->msr & 0xc0;
192
193    rtc->msr = 0;	/* Ensure timer registers accessible */
194
195    if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, IRQF_TIMER, "timer",
196                    NULL))
197	panic ("Couldn't register timer int");
198
199    rtc->t1cr_omr = 0x04;	/* Mode 2, ext clk */
200    rtc->t1msb = RTC_TIMER_COUNT >> 8;
201    rtc->t1lsb = RTC_TIMER_COUNT & 0xff;
202    rtc->irr_icr1 &= 0xef;	/* Route timer 1 to INTR pin */
203    rtc->msr = 0x40;		/* Access int.cntrl, etc */
204    rtc->pfr_icr0 = 0x80;	/* Just timer 1 ints enabled */
205    rtc->irr_icr1 = 0;
206    rtc->t1cr_omr = 0x0a;	/* INTR+T1 active lo, push-pull */
207    rtc->t0cr_rtmr &= 0xdf;	/* Stop timers in standby */
208    rtc->msr = 0;		/* Access timer 1 control */
209    rtc->t1cr_omr = 0x05;	/* Mode 2, ext clk, GO */
210
211    rtc->msr = msr;
212
213    clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ);
214
215    if (request_irq(BVME_IRQ_ABORT, bvme6000_abort_int, 0,
216				"abort", bvme6000_abort_int))
217	panic ("Couldn't register abort int");
218}
219
220
221/*
222 * NOTE:  Don't accept any readings within 5us of rollover, as
223 * the T1INT bit may be a little slow getting set.  There is also
224 * a fault in the chip, meaning that reads may produce invalid
225 * results...
226 */
227
228static u64 bvme6000_read_clk(struct clocksource *cs)
229{
230    unsigned long flags;
231    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
232    volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
233    unsigned char msr, msb;
234    unsigned char t1int, t1op;
235    u32 v = 800000, ov;
236
237    local_irq_save(flags);
238
239    msr = rtc->msr & 0xc0;
240    rtc->msr = 0;	/* Ensure timer registers accessible */
241
242    do {
243	ov = v;
244	t1int = rtc->msr & 0x20;
245	t1op  = pit->pcdr & 0x04;
246	rtc->t1cr_omr |= 0x40;		/* Latch timer1 */
247	msb = rtc->t1msb;		/* Read timer1 */
248	v = (msb << 8) | rtc->t1lsb;	/* Read timer1 */
249    } while (t1int != (rtc->msr & 0x20) ||
250		t1op != (pit->pcdr & 0x04) ||
251			abs(ov-v) > 80 ||
252				v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100));
253
254    v = RTC_TIMER_COUNT - v;
255    if (!t1op)				/* If in second half cycle.. */
256	v += RTC_TIMER_CYCLES / 2;
257    if (msb > 0 && t1int)
258	clk_offset = RTC_TIMER_CYCLES;
259    rtc->msr = msr;
260
261    v += clk_offset + clk_total;
262
263    local_irq_restore(flags);
264
265    return v;
266}
267
268/*
269 * Looks like op is non-zero for setting the clock, and zero for
270 * reading the clock.
271 *
272 *  struct hwclk_time {
273 *         unsigned        sec;       0..59
274 *         unsigned        min;       0..59
275 *         unsigned        hour;      0..23
276 *         unsigned        day;       1..31
277 *         unsigned        mon;       0..11
278 *         unsigned        year;      00...
279 *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
280 * };
281 */
282
283int bvme6000_hwclk(int op, struct rtc_time *t)
284{
285	volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
286	unsigned char msr = rtc->msr & 0xc0;
287
288	rtc->msr = 0x40;	/* Ensure clock and real-time-mode-register
289				 * are accessible */
290	if (op)
291	{	/* Write.... */
292		rtc->t0cr_rtmr = t->tm_year%4;
293		rtc->bcd_tenms = 0;
294		rtc->bcd_sec = bin2bcd(t->tm_sec);
295		rtc->bcd_min = bin2bcd(t->tm_min);
296		rtc->bcd_hr  = bin2bcd(t->tm_hour);
297		rtc->bcd_dom = bin2bcd(t->tm_mday);
298		rtc->bcd_mth = bin2bcd(t->tm_mon + 1);
299		rtc->bcd_year = bin2bcd(t->tm_year%100);
300		if (t->tm_wday >= 0)
301			rtc->bcd_dow = bin2bcd(t->tm_wday+1);
302		rtc->t0cr_rtmr = t->tm_year%4 | 0x08;
303	}
304	else
305	{	/* Read....  */
306		do {
307			t->tm_sec  = bcd2bin(rtc->bcd_sec);
308			t->tm_min  = bcd2bin(rtc->bcd_min);
309			t->tm_hour = bcd2bin(rtc->bcd_hr);
310			t->tm_mday = bcd2bin(rtc->bcd_dom);
311			t->tm_mon  = bcd2bin(rtc->bcd_mth)-1;
312			t->tm_year = bcd2bin(rtc->bcd_year);
313			if (t->tm_year < 70)
314				t->tm_year += 100;
315			t->tm_wday = bcd2bin(rtc->bcd_dow)-1;
316		} while (t->tm_sec != bcd2bin(rtc->bcd_sec));
317	}
318
319	rtc->msr = msr;
320
321	return 0;
322}
323