1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef __ASM_CSKY_CKMMUV1_H
4#define __ASM_CSKY_CKMMUV1_H
5#include <abi/reg_ops.h>
6
7static inline int read_mmu_index(void)
8{
9	return cprcr("cpcr0");
10}
11
12static inline void write_mmu_index(int value)
13{
14	cpwcr("cpcr0", value);
15}
16
17static inline int read_mmu_entrylo0(void)
18{
19	return cprcr("cpcr2") << 6;
20}
21
22static inline int read_mmu_entrylo1(void)
23{
24	return cprcr("cpcr3") << 6;
25}
26
27static inline void write_mmu_pagemask(int value)
28{
29	cpwcr("cpcr6", value);
30}
31
32static inline int read_mmu_entryhi(void)
33{
34	return cprcr("cpcr4");
35}
36
37static inline void write_mmu_entryhi(int value)
38{
39	cpwcr("cpcr4", value);
40}
41
42static inline unsigned long read_mmu_msa0(void)
43{
44	return cprcr("cpcr30");
45}
46
47static inline void write_mmu_msa0(unsigned long value)
48{
49	cpwcr("cpcr30", value);
50}
51
52static inline unsigned long read_mmu_msa1(void)
53{
54	return cprcr("cpcr31");
55}
56
57static inline void write_mmu_msa1(unsigned long value)
58{
59	cpwcr("cpcr31", value);
60}
61
62/*
63 * TLB operations.
64 */
65static inline void tlb_probe(void)
66{
67	cpwcr("cpcr8", 0x80000000);
68}
69
70static inline void tlb_read(void)
71{
72	cpwcr("cpcr8", 0x40000000);
73}
74
75static inline void tlb_invalid_all(void)
76{
77	cpwcr("cpcr8", 0x04000000);
78}
79
80
81static inline void local_tlb_invalid_all(void)
82{
83	tlb_invalid_all();
84}
85
86static inline void tlb_invalid_indexed(void)
87{
88	cpwcr("cpcr8", 0x02000000);
89}
90
91static inline void setup_pgd(pgd_t *pgd, int asid)
92{
93	cpwcr("cpcr29", __pa(pgd) | BIT(0));
94	write_mmu_entryhi(asid);
95}
96
97static inline pgd_t *get_pgd(void)
98{
99	return __va(cprcr("cpcr29") & ~BIT(0));
100}
101#endif /* __ASM_CSKY_CKMMUV1_H */
102