1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2016 - ARM Ltd
4 *
5 * stage2 page table helpers
6 */
7
8#ifndef __ARM64_S2_PGTABLE_H_
9#define __ARM64_S2_PGTABLE_H_
10
11#include <linux/pgtable.h>
12
13/*
14 * The hardware supports concatenation of up to 16 tables at stage2 entry
15 * level and we use the feature whenever possible, which means we resolve 4
16 * additional bits of address at the entry level.
17 *
18 * This implies, the total number of page table levels required for
19 * IPA_SHIFT at stage2 expected by the hardware can be calculated using
20 * the same logic used for the (non-collapsable) stage1 page tables but for
21 * (IPA_SHIFT - 4).
22 */
23#define stage2_pgtable_levels(ipa)	ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
24#define kvm_stage2_levels(mmu)		VTCR_EL2_LVLS((mmu)->vtcr)
25
26/*
27 * kvm_mmmu_cache_min_pages() is the number of pages required to install
28 * a stage-2 translation. We pre-allocate the entry level page table at
29 * the VM creation.
30 */
31#define kvm_mmu_cache_min_pages(mmu)	(kvm_stage2_levels(mmu) - 1)
32
33#endif	/* __ARM64_S2_PGTABLE_H_ */
34