1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
4 *
5 * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15	.irp		b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
16	.set		.Lq\b, \b
17	.set		.Lv\b\().2d, \b
18	.endr
19
20	.macro		sha512h, rd, rn, rm
21	.inst		0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
22	.endm
23
24	.macro		sha512h2, rd, rn, rm
25	.inst		0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
26	.endm
27
28	.macro		sha512su0, rd, rn
29	.inst		0xcec08000 | .L\rd | (.L\rn << 5)
30	.endm
31
32	.macro		sha512su1, rd, rn, rm
33	.inst		0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
34	.endm
35
36	/*
37	 * The SHA-512 round constants
38	 */
39	.section	".rodata", "a"
40	.align		4
41.Lsha512_rcon:
42	.quad		0x428a2f98d728ae22, 0x7137449123ef65cd
43	.quad		0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
44	.quad		0x3956c25bf348b538, 0x59f111f1b605d019
45	.quad		0x923f82a4af194f9b, 0xab1c5ed5da6d8118
46	.quad		0xd807aa98a3030242, 0x12835b0145706fbe
47	.quad		0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
48	.quad		0x72be5d74f27b896f, 0x80deb1fe3b1696b1
49	.quad		0x9bdc06a725c71235, 0xc19bf174cf692694
50	.quad		0xe49b69c19ef14ad2, 0xefbe4786384f25e3
51	.quad		0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
52	.quad		0x2de92c6f592b0275, 0x4a7484aa6ea6e483
53	.quad		0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
54	.quad		0x983e5152ee66dfab, 0xa831c66d2db43210
55	.quad		0xb00327c898fb213f, 0xbf597fc7beef0ee4
56	.quad		0xc6e00bf33da88fc2, 0xd5a79147930aa725
57	.quad		0x06ca6351e003826f, 0x142929670a0e6e70
58	.quad		0x27b70a8546d22ffc, 0x2e1b21385c26c926
59	.quad		0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
60	.quad		0x650a73548baf63de, 0x766a0abb3c77b2a8
61	.quad		0x81c2c92e47edaee6, 0x92722c851482353b
62	.quad		0xa2bfe8a14cf10364, 0xa81a664bbc423001
63	.quad		0xc24b8b70d0f89791, 0xc76c51a30654be30
64	.quad		0xd192e819d6ef5218, 0xd69906245565a910
65	.quad		0xf40e35855771202a, 0x106aa07032bbd1b8
66	.quad		0x19a4c116b8d2d0c8, 0x1e376c085141ab53
67	.quad		0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
68	.quad		0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
69	.quad		0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
70	.quad		0x748f82ee5defb2fc, 0x78a5636f43172f60
71	.quad		0x84c87814a1f0ab72, 0x8cc702081a6439ec
72	.quad		0x90befffa23631e28, 0xa4506cebde82bde9
73	.quad		0xbef9a3f7b2c67915, 0xc67178f2e372532b
74	.quad		0xca273eceea26619c, 0xd186b8c721c0c207
75	.quad		0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
76	.quad		0x06f067aa72176fba, 0x0a637dc5a2c898a6
77	.quad		0x113f9804bef90dae, 0x1b710b35131c471b
78	.quad		0x28db77f523047d84, 0x32caab7b40c72493
79	.quad		0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
80	.quad		0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
81	.quad		0x5fcb6fab3ad6faec, 0x6c44198c4a475817
82
83	.macro		dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4
84	.ifnb		\rc1
85	ld1		{v\rc1\().2d}, [x4], #16
86	.endif
87	add		v5.2d, v\rc0\().2d, v\in0\().2d
88	ext		v6.16b, v\i2\().16b, v\i3\().16b, #8
89	ext		v5.16b, v5.16b, v5.16b, #8
90	ext		v7.16b, v\i1\().16b, v\i2\().16b, #8
91	add		v\i3\().2d, v\i3\().2d, v5.2d
92	.ifnb		\in1
93	ext		v5.16b, v\in3\().16b, v\in4\().16b, #8
94	sha512su0	v\in0\().2d, v\in1\().2d
95	.endif
96	sha512h		q\i3, q6, v7.2d
97	.ifnb		\in1
98	sha512su1	v\in0\().2d, v\in2\().2d, v5.2d
99	.endif
100	add		v\i4\().2d, v\i1\().2d, v\i3\().2d
101	sha512h2	q\i3, q\i1, v\i0\().2d
102	.endm
103
104	/*
105	 * int __sha512_ce_transform(struct sha512_state *sst, u8 const *src,
106	 *			     int blocks)
107	 */
108	.text
109SYM_FUNC_START(__sha512_ce_transform)
110	/* load state */
111	ld1		{v8.2d-v11.2d}, [x0]
112
113	/* load first 4 round constants */
114	adr_l		x3, .Lsha512_rcon
115	ld1		{v20.2d-v23.2d}, [x3], #64
116
117	/* load input */
1180:	ld1		{v12.2d-v15.2d}, [x1], #64
119	ld1		{v16.2d-v19.2d}, [x1], #64
120	sub		w2, w2, #1
121
122CPU_LE(	rev64		v12.16b, v12.16b	)
123CPU_LE(	rev64		v13.16b, v13.16b	)
124CPU_LE(	rev64		v14.16b, v14.16b	)
125CPU_LE(	rev64		v15.16b, v15.16b	)
126CPU_LE(	rev64		v16.16b, v16.16b	)
127CPU_LE(	rev64		v17.16b, v17.16b	)
128CPU_LE(	rev64		v18.16b, v18.16b	)
129CPU_LE(	rev64		v19.16b, v19.16b	)
130
131	mov		x4, x3				// rc pointer
132
133	mov		v0.16b, v8.16b
134	mov		v1.16b, v9.16b
135	mov		v2.16b, v10.16b
136	mov		v3.16b, v11.16b
137
138	// v0  ab  cd  --  ef  gh  ab
139	// v1  cd  --  ef  gh  ab  cd
140	// v2  ef  gh  ab  cd  --  ef
141	// v3  gh  ab  cd  --  ef  gh
142	// v4  --  ef  gh  ab  cd  --
143
144	dround		0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17
145	dround		3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18
146	dround		2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19
147	dround		4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12
148	dround		1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13
149
150	dround		0, 1, 2, 3, 4, 25, 29, 17, 18, 16, 13, 14
151	dround		3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15
152	dround		2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16
153	dround		4, 2, 0, 1, 3, 28, 24, 12, 13, 19, 16, 17
154	dround		1, 4, 3, 0, 2, 29, 25, 13, 14, 12, 17, 18
155
156	dround		0, 1, 2, 3, 4, 30, 26, 14, 15, 13, 18, 19
157	dround		3, 0, 4, 2, 1, 31, 27, 15, 16, 14, 19, 12
158	dround		2, 3, 1, 4, 0, 24, 28, 16, 17, 15, 12, 13
159	dround		4, 2, 0, 1, 3, 25, 29, 17, 18, 16, 13, 14
160	dround		1, 4, 3, 0, 2, 26, 30, 18, 19, 17, 14, 15
161
162	dround		0, 1, 2, 3, 4, 27, 31, 19, 12, 18, 15, 16
163	dround		3, 0, 4, 2, 1, 28, 24, 12, 13, 19, 16, 17
164	dround		2, 3, 1, 4, 0, 29, 25, 13, 14, 12, 17, 18
165	dround		4, 2, 0, 1, 3, 30, 26, 14, 15, 13, 18, 19
166	dround		1, 4, 3, 0, 2, 31, 27, 15, 16, 14, 19, 12
167
168	dround		0, 1, 2, 3, 4, 24, 28, 16, 17, 15, 12, 13
169	dround		3, 0, 4, 2, 1, 25, 29, 17, 18, 16, 13, 14
170	dround		2, 3, 1, 4, 0, 26, 30, 18, 19, 17, 14, 15
171	dround		4, 2, 0, 1, 3, 27, 31, 19, 12, 18, 15, 16
172	dround		1, 4, 3, 0, 2, 28, 24, 12, 13, 19, 16, 17
173
174	dround		0, 1, 2, 3, 4, 29, 25, 13, 14, 12, 17, 18
175	dround		3, 0, 4, 2, 1, 30, 26, 14, 15, 13, 18, 19
176	dround		2, 3, 1, 4, 0, 31, 27, 15, 16, 14, 19, 12
177	dround		4, 2, 0, 1, 3, 24, 28, 16, 17, 15, 12, 13
178	dround		1, 4, 3, 0, 2, 25, 29, 17, 18, 16, 13, 14
179
180	dround		0, 1, 2, 3, 4, 26, 30, 18, 19, 17, 14, 15
181	dround		3, 0, 4, 2, 1, 27, 31, 19, 12, 18, 15, 16
182	dround		2, 3, 1, 4, 0, 28, 24, 12
183	dround		4, 2, 0, 1, 3, 29, 25, 13
184	dround		1, 4, 3, 0, 2, 30, 26, 14
185
186	dround		0, 1, 2, 3, 4, 31, 27, 15
187	dround		3, 0, 4, 2, 1, 24,   , 16
188	dround		2, 3, 1, 4, 0, 25,   , 17
189	dround		4, 2, 0, 1, 3, 26,   , 18
190	dround		1, 4, 3, 0, 2, 27,   , 19
191
192	/* update state */
193	add		v8.2d, v8.2d, v0.2d
194	add		v9.2d, v9.2d, v1.2d
195	add		v10.2d, v10.2d, v2.2d
196	add		v11.2d, v11.2d, v3.2d
197
198	cond_yield	3f, x4, x5
199	/* handled all input blocks? */
200	cbnz		w2, 0b
201
202	/* store new state */
2033:	st1		{v8.2d-v11.2d}, [x0]
204	mov		w0, w2
205	ret
206SYM_FUNC_END(__sha512_ce_transform)
207