1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 wkup_conf: bus@43000000 { 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 ranges = <0x0 0x00 0x43000000 0x20000>; 42 43 chipid: chipid@14 { 44 compatible = "ti,am654-chipid"; 45 reg = <0x14 0x4>; 46 }; 47 }; 48 49 secure_proxy_sa3: mailbox@43600000 { 50 compatible = "ti,am654-secure-proxy"; 51 #mbox-cells = <1>; 52 reg-names = "target_data", "rt", "scfg"; 53 reg = <0x00 0x43600000 0x00 0x10000>, 54 <0x00 0x44880000 0x00 0x20000>, 55 <0x00 0x44860000 0x00 0x20000>; 56 /* 57 * Marked Disabled: 58 * Node is incomplete as it is meant for bootloaders and 59 * firmware on non-MPU processors 60 */ 61 status = "disabled"; 62 }; 63 64 mcu_ram: sram@41c00000 { 65 compatible = "mmio-sram"; 66 reg = <0x00 0x41c00000 0x00 0x100000>; 67 ranges = <0x00 0x00 0x41c00000 0x100000>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 }; 71 72 wkup_pmx0: pinctrl@4301c000 { 73 compatible = "pinctrl-single"; 74 /* Proxy 0 addressing */ 75 reg = <0x00 0x4301c000 0x00 0x034>; 76 #pinctrl-cells = <1>; 77 pinctrl-single,register-width = <32>; 78 pinctrl-single,function-mask = <0xffffffff>; 79 }; 80 81 wkup_pmx1: pinctrl@4301c038 { 82 compatible = "pinctrl-single"; 83 /* Proxy 0 addressing */ 84 reg = <0x00 0x4301c038 0x00 0x02C>; 85 #pinctrl-cells = <1>; 86 pinctrl-single,register-width = <32>; 87 pinctrl-single,function-mask = <0xffffffff>; 88 }; 89 90 wkup_pmx2: pinctrl@4301c068 { 91 compatible = "pinctrl-single"; 92 /* Proxy 0 addressing */ 93 reg = <0x00 0x4301c068 0x00 0x120>; 94 #pinctrl-cells = <1>; 95 pinctrl-single,register-width = <32>; 96 pinctrl-single,function-mask = <0xffffffff>; 97 }; 98 99 wkup_pmx3: pinctrl@4301c190 { 100 compatible = "pinctrl-single"; 101 /* Proxy 0 addressing */ 102 reg = <0x00 0x4301c190 0x00 0x004>; 103 #pinctrl-cells = <1>; 104 pinctrl-single,register-width = <32>; 105 pinctrl-single,function-mask = <0xffffffff>; 106 }; 107 108 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 109 mcu_timerio_input: pinctrl@40f04200 { 110 compatible = "pinctrl-single"; 111 reg = <0x00 0x40f04200 0x00 0x28>; 112 #pinctrl-cells = <1>; 113 pinctrl-single,register-width = <32>; 114 pinctrl-single,function-mask = <0x0000000f>; 115 /* Non-MPU Firmware usage */ 116 status = "reserved"; 117 }; 118 119 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 120 mcu_timerio_output: pinctrl@40f04280 { 121 compatible = "pinctrl-single"; 122 reg = <0x00 0x40f04280 0x00 0x28>; 123 #pinctrl-cells = <1>; 124 pinctrl-single,register-width = <32>; 125 pinctrl-single,function-mask = <0x0000000f>; 126 /* Non-MPU Firmware usage */ 127 status = "reserved"; 128 }; 129 130 wkup_gpio_intr: interrupt-controller@42200000 { 131 compatible = "ti,sci-intr"; 132 reg = <0x00 0x42200000 0x00 0x400>; 133 ti,intr-trigger-type = <1>; 134 interrupt-controller; 135 interrupt-parent = <&gic500>; 136 #interrupt-cells = <1>; 137 ti,sci = <&sms>; 138 ti,sci-dev-id = <125>; 139 ti,interrupt-ranges = <16 960 16>; 140 }; 141 142 mcu_conf: syscon@40f00000 { 143 compatible = "syscon", "simple-mfd"; 144 reg = <0x0 0x40f00000 0x0 0x20000>; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0x0 0x0 0x40f00000 0x20000>; 148 149 phy_gmii_sel: phy@4040 { 150 compatible = "ti,am654-phy-gmii-sel"; 151 reg = <0x4040 0x4>; 152 #phy-cells = <1>; 153 }; 154 155 }; 156 157 mcu_timer0: timer@40400000 { 158 compatible = "ti,am654-timer"; 159 reg = <0x00 0x40400000 0x00 0x400>; 160 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&k3_clks 35 1>; 162 clock-names = "fck"; 163 assigned-clocks = <&k3_clks 35 1>; 164 assigned-clock-parents = <&k3_clks 35 2>; 165 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 166 ti,timer-pwm; 167 /* Non-MPU Firmware usage */ 168 status = "reserved"; 169 }; 170 171 mcu_timer1: timer@40410000 { 172 compatible = "ti,am654-timer"; 173 reg = <0x00 0x40410000 0x00 0x400>; 174 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&k3_clks 83 1>; 176 clock-names = "fck"; 177 assigned-clocks = <&k3_clks 83 1>; 178 assigned-clock-parents = <&k3_clks 83 2>; 179 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 180 ti,timer-pwm; 181 /* Non-MPU Firmware usage */ 182 status = "reserved"; 183 }; 184 185 mcu_timer2: timer@40420000 { 186 compatible = "ti,am654-timer"; 187 reg = <0x00 0x40420000 0x00 0x400>; 188 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&k3_clks 84 1>; 190 clock-names = "fck"; 191 assigned-clocks = <&k3_clks 84 1>; 192 assigned-clock-parents = <&k3_clks 84 2>; 193 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 194 ti,timer-pwm; 195 /* Non-MPU Firmware usage */ 196 status = "reserved"; 197 }; 198 199 mcu_timer3: timer@40430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x40430000 0x00 0x400>; 202 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 85 1>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 85 1>; 206 assigned-clock-parents = <&k3_clks 85 2>; 207 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 /* Non-MPU Firmware usage */ 210 status = "reserved"; 211 }; 212 213 mcu_timer4: timer@40440000 { 214 compatible = "ti,am654-timer"; 215 reg = <0x00 0x40440000 0x00 0x400>; 216 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&k3_clks 86 1>; 218 clock-names = "fck"; 219 assigned-clocks = <&k3_clks 86 1>; 220 assigned-clock-parents = <&k3_clks 86 2>; 221 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 222 ti,timer-pwm; 223 /* Non-MPU Firmware usage */ 224 status = "reserved"; 225 }; 226 227 mcu_timer5: timer@40450000 { 228 compatible = "ti,am654-timer"; 229 reg = <0x00 0x40450000 0x00 0x400>; 230 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 87 1>; 232 clock-names = "fck"; 233 assigned-clocks = <&k3_clks 87 1>; 234 assigned-clock-parents = <&k3_clks 87 2>; 235 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 236 ti,timer-pwm; 237 /* Non-MPU Firmware usage */ 238 status = "reserved"; 239 }; 240 241 mcu_timer6: timer@40460000 { 242 compatible = "ti,am654-timer"; 243 reg = <0x00 0x40460000 0x00 0x400>; 244 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&k3_clks 88 1>; 246 clock-names = "fck"; 247 assigned-clocks = <&k3_clks 88 1>; 248 assigned-clock-parents = <&k3_clks 88 2>; 249 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 250 ti,timer-pwm; 251 /* Non-MPU Firmware usage */ 252 status = "reserved"; 253 }; 254 255 mcu_timer7: timer@40470000 { 256 compatible = "ti,am654-timer"; 257 reg = <0x00 0x40470000 0x00 0x400>; 258 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&k3_clks 89 1>; 260 clock-names = "fck"; 261 assigned-clocks = <&k3_clks 89 1>; 262 assigned-clock-parents = <&k3_clks 89 2>; 263 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 264 ti,timer-pwm; 265 /* Non-MPU Firmware usage */ 266 status = "reserved"; 267 }; 268 269 mcu_timer8: timer@40480000 { 270 compatible = "ti,am654-timer"; 271 reg = <0x00 0x40480000 0x00 0x400>; 272 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&k3_clks 90 1>; 274 clock-names = "fck"; 275 assigned-clocks = <&k3_clks 90 1>; 276 assigned-clock-parents = <&k3_clks 90 2>; 277 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 278 ti,timer-pwm; 279 /* Non-MPU Firmware usage */ 280 status = "reserved"; 281 }; 282 283 mcu_timer9: timer@40490000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x40490000 0x00 0x400>; 286 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 91 1>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 91 1>; 290 assigned-clock-parents = <&k3_clks 91 2>; 291 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 /* Non-MPU Firmware usage */ 294 status = "reserved"; 295 }; 296 297 wkup_uart0: serial@42300000 { 298 compatible = "ti,j721e-uart", "ti,am654-uart"; 299 reg = <0x00 0x42300000 0x00 0x200>; 300 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 301 current-speed = <115200>; 302 clocks = <&k3_clks 359 3>; 303 clock-names = "fclk"; 304 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 305 status = "disabled"; 306 }; 307 308 mcu_uart0: serial@40a00000 { 309 compatible = "ti,j721e-uart", "ti,am654-uart"; 310 reg = <0x00 0x40a00000 0x00 0x200>; 311 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 312 current-speed = <115200>; 313 clocks = <&k3_clks 149 3>; 314 clock-names = "fclk"; 315 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 316 status = "disabled"; 317 }; 318 319 wkup_gpio0: gpio@42110000 { 320 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 321 reg = <0x00 0x42110000 0x00 0x100>; 322 gpio-controller; 323 #gpio-cells = <2>; 324 interrupt-parent = <&wkup_gpio_intr>; 325 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 ti,ngpio = <89>; 329 ti,davinci-gpio-unbanked = <0>; 330 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 331 clocks = <&k3_clks 115 0>; 332 clock-names = "gpio"; 333 status = "disabled"; 334 }; 335 336 wkup_gpio1: gpio@42100000 { 337 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 338 reg = <0x00 0x42100000 0x00 0x100>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-parent = <&wkup_gpio_intr>; 342 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 ti,ngpio = <89>; 346 ti,davinci-gpio-unbanked = <0>; 347 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 348 clocks = <&k3_clks 116 0>; 349 clock-names = "gpio"; 350 status = "disabled"; 351 }; 352 353 wkup_i2c0: i2c@42120000 { 354 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 355 reg = <0x00 0x42120000 0x00 0x100>; 356 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clocks = <&k3_clks 223 1>; 360 clock-names = "fck"; 361 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 362 status = "disabled"; 363 }; 364 365 mcu_i2c0: i2c@40b00000 { 366 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 367 reg = <0x00 0x40b00000 0x00 0x100>; 368 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&k3_clks 221 1>; 372 clock-names = "fck"; 373 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 374 status = "disabled"; 375 }; 376 377 mcu_i2c1: i2c@40b10000 { 378 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 379 reg = <0x00 0x40b10000 0x00 0x100>; 380 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&k3_clks 222 1>; 384 clock-names = "fck"; 385 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 386 status = "disabled"; 387 }; 388 389 mcu_mcan0: can@40528000 { 390 compatible = "bosch,m_can"; 391 reg = <0x00 0x40528000 0x00 0x200>, 392 <0x00 0x40500000 0x00 0x8000>; 393 reg-names = "m_can", "message_ram"; 394 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 395 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 396 clock-names = "hclk", "cclk"; 397 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 399 interrupt-names = "int0", "int1"; 400 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 401 status = "disabled"; 402 }; 403 404 mcu_mcan1: can@40568000 { 405 compatible = "bosch,m_can"; 406 reg = <0x00 0x40568000 0x00 0x200>, 407 <0x00 0x40540000 0x00 0x8000>; 408 reg-names = "m_can", "message_ram"; 409 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 410 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 411 clock-names = "hclk", "cclk"; 412 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-names = "int0", "int1"; 415 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 416 status = "disabled"; 417 }; 418 419 mcu_spi0: spi@40300000 { 420 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 421 reg = <0x00 0x040300000 0x00 0x400>; 422 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 347 0>; 427 status = "disabled"; 428 }; 429 430 mcu_spi1: spi@40310000 { 431 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 432 reg = <0x00 0x040310000 0x00 0x400>; 433 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 437 clocks = <&k3_clks 348 0>; 438 status = "disabled"; 439 }; 440 441 mcu_spi2: spi@40320000 { 442 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 443 reg = <0x00 0x040320000 0x00 0x400>; 444 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 448 clocks = <&k3_clks 349 0>; 449 status = "disabled"; 450 }; 451 452 mcu_navss: bus@28380000 { 453 compatible = "simple-bus"; 454 #address-cells = <2>; 455 #size-cells = <2>; 456 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 457 dma-coherent; 458 dma-ranges; 459 460 ti,sci-dev-id = <267>; 461 462 mcu_ringacc: ringacc@2b800000 { 463 compatible = "ti,am654-navss-ringacc"; 464 reg = <0x0 0x2b800000 0x0 0x400000>, 465 <0x0 0x2b000000 0x0 0x400000>, 466 <0x0 0x28590000 0x0 0x100>, 467 <0x0 0x2a500000 0x0 0x40000>, 468 <0x0 0x28440000 0x0 0x40000>; 469 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 470 ti,num-rings = <286>; 471 ti,sci-rm-range-gp-rings = <0x1>; 472 ti,sci = <&sms>; 473 ti,sci-dev-id = <272>; 474 msi-parent = <&main_udmass_inta>; 475 }; 476 477 mcu_udmap: dma-controller@285c0000 { 478 compatible = "ti,j721e-navss-mcu-udmap"; 479 reg = <0x0 0x285c0000 0x0 0x100>, 480 <0x0 0x2a800000 0x0 0x40000>, 481 <0x0 0x2aa00000 0x0 0x40000>, 482 <0x0 0x284a0000 0x0 0x4000>, 483 <0x0 0x284c0000 0x0 0x4000>, 484 <0x0 0x28400000 0x0 0x2000>; 485 reg-names = "gcfg", "rchanrt", "tchanrt", 486 "tchan", "rchan", "rflow"; 487 msi-parent = <&main_udmass_inta>; 488 #dma-cells = <1>; 489 490 ti,sci = <&sms>; 491 ti,sci-dev-id = <273>; 492 ti,ringacc = <&mcu_ringacc>; 493 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 494 <0x0f>; /* TX_HCHAN */ 495 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 496 <0x0b>; /* RX_HCHAN */ 497 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 498 }; 499 }; 500 501 secure_proxy_mcu: mailbox@2a480000 { 502 compatible = "ti,am654-secure-proxy"; 503 #mbox-cells = <1>; 504 reg-names = "target_data", "rt", "scfg"; 505 reg = <0x00 0x2a480000 0x00 0x80000>, 506 <0x00 0x2a380000 0x00 0x80000>, 507 <0x00 0x2a400000 0x00 0x80000>; 508 /* 509 * Marked Disabled: 510 * Node is incomplete as it is meant for bootloaders and 511 * firmware on non-MPU processors 512 */ 513 status = "disabled"; 514 }; 515 516 mcu_cpsw: ethernet@46000000 { 517 compatible = "ti,j721e-cpsw-nuss"; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 reg = <0x0 0x46000000 0x0 0x200000>; 521 reg-names = "cpsw_nuss"; 522 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 523 dma-coherent; 524 clocks = <&k3_clks 29 28>; 525 clock-names = "fck"; 526 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 527 528 dmas = <&mcu_udmap 0xf000>, 529 <&mcu_udmap 0xf001>, 530 <&mcu_udmap 0xf002>, 531 <&mcu_udmap 0xf003>, 532 <&mcu_udmap 0xf004>, 533 <&mcu_udmap 0xf005>, 534 <&mcu_udmap 0xf006>, 535 <&mcu_udmap 0xf007>, 536 <&mcu_udmap 0x7000>; 537 dma-names = "tx0", "tx1", "tx2", "tx3", 538 "tx4", "tx5", "tx6", "tx7", 539 "rx"; 540 541 ethernet-ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 cpsw_port1: port@1 { 546 reg = <1>; 547 ti,mac-only; 548 label = "port1"; 549 ti,syscon-efuse = <&mcu_conf 0x200>; 550 phys = <&phy_gmii_sel 1>; 551 }; 552 }; 553 554 davinci_mdio: mdio@f00 { 555 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 556 reg = <0x0 0xf00 0x0 0x100>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 clocks = <&k3_clks 29 28>; 560 clock-names = "fck"; 561 bus_freq = <1000000>; 562 }; 563 564 cpts@3d000 { 565 compatible = "ti,am65-cpts"; 566 reg = <0x0 0x3d000 0x0 0x400>; 567 clocks = <&k3_clks 29 3>; 568 clock-names = "cpts"; 569 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ 570 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ 571 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "cpts"; 573 ti,cpts-ext-ts-inputs = <4>; 574 ti,cpts-periodic-outputs = <2>; 575 }; 576 }; 577 578 tscadc0: tscadc@40200000 { 579 compatible = "ti,am3359-tscadc"; 580 reg = <0x00 0x40200000 0x00 0x1000>; 581 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 582 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 583 clocks = <&k3_clks 0 0>; 584 assigned-clocks = <&k3_clks 0 2>; 585 assigned-clock-rates = <60000000>; 586 clock-names = "fck"; 587 dmas = <&main_udmap 0x7400>, 588 <&main_udmap 0x7401>; 589 dma-names = "fifo0", "fifo1"; 590 status = "disabled"; 591 592 adc { 593 #io-channel-cells = <1>; 594 compatible = "ti,am3359-adc"; 595 }; 596 }; 597 598 tscadc1: tscadc@40210000 { 599 compatible = "ti,am3359-tscadc"; 600 reg = <0x00 0x40210000 0x00 0x1000>; 601 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 602 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 603 clocks = <&k3_clks 1 0>; 604 assigned-clocks = <&k3_clks 1 2>; 605 assigned-clock-rates = <60000000>; 606 clock-names = "fck"; 607 dmas = <&main_udmap 0x7402>, 608 <&main_udmap 0x7403>; 609 dma-names = "fifo0", "fifo1"; 610 status = "disabled"; 611 612 adc { 613 #io-channel-cells = <1>; 614 compatible = "ti,am3359-adc"; 615 }; 616 }; 617 618 fss: bus@47000000 { 619 compatible = "simple-bus"; 620 #address-cells = <2>; 621 #size-cells = <2>; 622 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 623 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 624 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 625 626 ospi0: spi@47040000 { 627 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 628 reg = <0x00 0x47040000 0x00 0x100>, 629 <0x05 0x00000000 0x01 0x00000000>; 630 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 631 cdns,fifo-depth = <256>; 632 cdns,fifo-width = <4>; 633 cdns,trigger-address = <0x0>; 634 clocks = <&k3_clks 109 5>; 635 assigned-clocks = <&k3_clks 109 5>; 636 assigned-clock-parents = <&k3_clks 109 7>; 637 assigned-clock-rates = <166666666>; 638 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 status = "disabled"; /* Needs pinmux */ 643 }; 644 645 ospi1: spi@47050000 { 646 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 647 reg = <0x00 0x47050000 0x00 0x100>, 648 <0x07 0x00000000 0x01 0x00000000>; 649 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 650 cdns,fifo-depth = <256>; 651 cdns,fifo-width = <4>; 652 cdns,trigger-address = <0x0>; 653 clocks = <&k3_clks 110 5>; 654 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 658 status = "disabled"; /* Needs pinmux */ 659 }; 660 }; 661 662 wkup_vtm0: temperature-sensor@42040000 { 663 compatible = "ti,j7200-vtm"; 664 reg = <0x00 0x42040000 0x0 0x350>, 665 <0x00 0x42050000 0x0 0x350>; 666 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; 667 #thermal-sensor-cells = <1>; 668 }; 669 670 mcu_r5fss0: r5fss@41000000 { 671 compatible = "ti,j721s2-r5fss"; 672 ti,cluster-mode = <1>; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 ranges = <0x41000000 0x00 0x41000000 0x20000>, 676 <0x41400000 0x00 0x41400000 0x20000>; 677 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 678 679 mcu_r5fss0_core0: r5f@41000000 { 680 compatible = "ti,j721s2-r5f"; 681 reg = <0x41000000 0x00010000>, 682 <0x41010000 0x00010000>; 683 reg-names = "atcm", "btcm"; 684 ti,sci = <&sms>; 685 ti,sci-dev-id = <284>; 686 ti,sci-proc-ids = <0x01 0xff>; 687 resets = <&k3_reset 284 1>; 688 firmware-name = "j721s2-mcu-r5f0_0-fw"; 689 ti,atcm-enable = <1>; 690 ti,btcm-enable = <1>; 691 ti,loczrama = <1>; 692 }; 693 694 mcu_r5fss0_core1: r5f@41400000 { 695 compatible = "ti,j721s2-r5f"; 696 reg = <0x41400000 0x00010000>, 697 <0x41410000 0x00010000>; 698 reg-names = "atcm", "btcm"; 699 ti,sci = <&sms>; 700 ti,sci-dev-id = <285>; 701 ti,sci-proc-ids = <0x02 0xff>; 702 resets = <&k3_reset 285 1>; 703 firmware-name = "j721s2-mcu-r5f0_1-fw"; 704 ti,atcm-enable = <1>; 705 ti,btcm-enable = <1>; 706 ti,loczrama = <1>; 707 }; 708 }; 709 710 mcu_esm: esm@40800000 { 711 compatible = "ti,j721e-esm"; 712 reg = <0x00 0x40800000 0x00 0x1000>; 713 ti,esm-pins = <95>; 714 bootph-pre-ram; 715 }; 716 717 wkup_esm: esm@42080000 { 718 compatible = "ti,j721e-esm"; 719 reg = <0x00 0x42080000 0x00 0x1000>; 720 ti,esm-pins = <63>; 721 bootph-pre-ram; 722 }; 723 724 /* 725 * The 2 RTI instances are couple with MCU R5Fs so keeping them 726 * reserved as these will be used by their respective firmware 727 */ 728 mcu_watchdog0: watchdog@40600000 { 729 compatible = "ti,j7-rti-wdt"; 730 reg = <0x00 0x40600000 0x00 0x100>; 731 clocks = <&k3_clks 295 1>; 732 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 733 assigned-clocks = <&k3_clks 295 1>; 734 assigned-clock-parents = <&k3_clks 295 5>; 735 /* reserved for MCU_R5F0_0 */ 736 status = "reserved"; 737 }; 738 739 mcu_watchdog1: watchdog@40610000 { 740 compatible = "ti,j7-rti-wdt"; 741 reg = <0x00 0x40610000 0x00 0x100>; 742 clocks = <&k3_clks 296 1>; 743 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; 744 assigned-clocks = <&k3_clks 296 1>; 745 assigned-clock-parents = <&k3_clks 296 5>; 746 /* reserved for MCU_R5F0_1 */ 747 status = "reserved"; 748 }; 749}; 750