1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721s2.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12	memory@80000000 {
13		device_type = "memory";
14		/* 16 GB RAM */
15		reg = <0x00 0x80000000 0x00 0x80000000>,
16		      <0x08 0x80000000 0x03 0x80000000>;
17	};
18
19	reserved_memory: reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		secure_ddr: optee@9e800000 {
25			reg = <0x00 0x9e800000 0x00 0x01800000>;
26			no-map;
27		};
28
29		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30			compatible = "shared-dma-pool";
31			reg = <0x00 0xa0000000 0x00 0x100000>;
32			no-map;
33		};
34
35		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
36			compatible = "shared-dma-pool";
37			reg = <0x00 0xa0100000 0x00 0xf00000>;
38			no-map;
39		};
40
41		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
42			compatible = "shared-dma-pool";
43			reg = <0x00 0xa1000000 0x00 0x100000>;
44			no-map;
45		};
46
47		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
48			compatible = "shared-dma-pool";
49			reg = <0x00 0xa1100000 0x00 0xf00000>;
50			no-map;
51		};
52
53		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x00 0xa2000000 0x00 0x100000>;
56			no-map;
57		};
58
59		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
60			compatible = "shared-dma-pool";
61			reg = <0x00 0xa2100000 0x00 0xf00000>;
62			no-map;
63		};
64
65		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
66			compatible = "shared-dma-pool";
67			reg = <0x00 0xa3000000 0x00 0x100000>;
68			no-map;
69		};
70
71		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
72			compatible = "shared-dma-pool";
73			reg = <0x00 0xa3100000 0x00 0xf00000>;
74			no-map;
75		};
76
77		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
78			compatible = "shared-dma-pool";
79			reg = <0x00 0xa4000000 0x00 0x100000>;
80			no-map;
81		};
82
83		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
84			compatible = "shared-dma-pool";
85			reg = <0x00 0xa4100000 0x00 0xf00000>;
86			no-map;
87		};
88
89		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
90			compatible = "shared-dma-pool";
91			reg = <0x00 0xa5000000 0x00 0x100000>;
92			no-map;
93		};
94
95		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
96			compatible = "shared-dma-pool";
97			reg = <0x00 0xa5100000 0x00 0xf00000>;
98			no-map;
99		};
100
101		c71_0_dma_memory_region: c71-dma-memory@a6000000 {
102			compatible = "shared-dma-pool";
103			reg = <0x00 0xa6000000 0x00 0x100000>;
104			no-map;
105		};
106
107		c71_0_memory_region: c71-memory@a6100000 {
108			compatible = "shared-dma-pool";
109			reg = <0x00 0xa6100000 0x00 0xf00000>;
110			no-map;
111		};
112
113		c71_1_dma_memory_region: c71-dma-memory@a7000000 {
114			compatible = "shared-dma-pool";
115			reg = <0x00 0xa7000000 0x00 0x100000>;
116			no-map;
117		};
118
119		c71_1_memory_region: c71-memory@a7100000 {
120			compatible = "shared-dma-pool";
121			reg = <0x00 0xa7100000 0x00 0xf00000>;
122			no-map;
123		};
124
125		rtos_ipc_memory_region: ipc-memories@a8000000 {
126			reg = <0x00 0xa8000000 0x00 0x01c00000>;
127			alignment = <0x1000>;
128			no-map;
129		};
130	};
131};
132
133&wkup_pmx2 {
134	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
135		pinctrl-single,pins = <
136			J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
137			J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
138		>;
139	};
140};
141
142&wkup_i2c0 {
143	status = "okay";
144	pinctrl-names = "default";
145	pinctrl-0 = <&wkup_i2c0_pins_default>;
146	clock-frequency = <400000>;
147
148	eeprom@51 {
149		/* AT24C512C-MAHM-T */
150		compatible = "atmel,24c512";
151		reg = <0x51>;
152	};
153};
154
155&mailbox0_cluster0 {
156	status = "okay";
157	interrupts = <436>;
158	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
159		ti,mbox-rx = <0 0 0>;
160		ti,mbox-tx = <1 0 0>;
161	};
162
163	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
164		ti,mbox-rx = <2 0 0>;
165		ti,mbox-tx = <3 0 0>;
166	};
167};
168
169&mailbox0_cluster1 {
170	status = "okay";
171	interrupts = <432>;
172	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
173		ti,mbox-rx = <0 0 0>;
174		ti,mbox-tx = <1 0 0>;
175	};
176
177	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
178		ti,mbox-rx = <2 0 0>;
179		ti,mbox-tx = <3 0 0>;
180	};
181};
182
183&mailbox0_cluster2 {
184	status = "okay";
185	interrupts = <428>;
186	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
187		ti,mbox-rx = <0 0 0>;
188		ti,mbox-tx = <1 0 0>;
189	};
190
191	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
192		ti,mbox-rx = <2 0 0>;
193		ti,mbox-tx = <3 0 0>;
194	};
195};
196
197&mailbox0_cluster4 {
198	status = "okay";
199	interrupts = <420>;
200	mbox_c71_0: mbox-c71-0 {
201		ti,mbox-rx = <0 0 0>;
202		ti,mbox-tx = <1 0 0>;
203	};
204
205	mbox_c71_1: mbox-c71-1 {
206		ti,mbox-rx = <2 0 0>;
207		ti,mbox-tx = <3 0 0>;
208	};
209};
210
211&mcu_r5fss0_core0 {
212	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
213	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
214			<&mcu_r5fss0_core0_memory_region>;
215};
216
217&mcu_r5fss0_core1 {
218	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
219	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
220			<&mcu_r5fss0_core1_memory_region>;
221};
222
223&main_r5fss0_core0 {
224	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
225	memory-region = <&main_r5fss0_core0_dma_memory_region>,
226			<&main_r5fss0_core0_memory_region>;
227};
228
229&main_r5fss0_core1 {
230	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
231	memory-region = <&main_r5fss0_core1_dma_memory_region>,
232			<&main_r5fss0_core1_memory_region>;
233};
234
235&main_r5fss1_core0 {
236	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
237	memory-region = <&main_r5fss1_core0_dma_memory_region>,
238			<&main_r5fss1_core0_memory_region>;
239};
240
241&main_r5fss1_core1 {
242	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
243	memory-region = <&main_r5fss1_core1_dma_memory_region>,
244			<&main_r5fss1_core1_memory_region>;
245};
246
247&c71_0 {
248	status = "okay";
249	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
250	memory-region = <&c71_0_dma_memory_region>,
251			<&c71_0_memory_region>;
252};
253
254&c71_1 {
255	status = "okay";
256	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
257	memory-region = <&c71_1_dma_memory_region>,
258			<&c71_1_memory_region>;
259};
260