1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include "mt8186.dtsi" 7#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/input/gpio-keys.h> 11#include <dt-bindings/regulator/mediatek,mt6397-regulator.h> 12 13/ { 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c5 = &i2c5; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 /* The size should be filled in by the bootloader. */ 32 reg = <0 0x40000000 0 0>; 33 }; 34 35 backlight_lcd0: backlight-lcd0 { 36 compatible = "pwm-backlight"; 37 pwms = <&pwm0 0 500000>; 38 power-supply = <&ppvar_sys>; 39 enable-gpios = <&pio 152 0>; 40 brightness-levels = <0 1023>; 41 num-interpolated-steps = <1023>; 42 default-brightness-level = <576>; 43 }; 44 45 bt-sco-codec { 46 compatible = "linux,bt-sco"; 47 #sound-dai-cells = <0>; 48 }; 49 50 dmic-codec { 51 compatible = "dmic-codec"; 52 #sound-dai-cells = <0>; 53 num-channels = <2>; 54 wakeup-delay-ms = <50>; 55 }; 56 57 gpio_keys: gpio-keys { 58 compatible = "gpio-keys"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pen_eject>; 61 62 pen_insert: pen-insert-switch { 63 label = "Pen Insert"; 64 /* Insert = low, eject = high */ 65 gpios = <&pio 18 GPIO_ACTIVE_LOW>; 66 wakeup-event-action = <EV_ACT_DEASSERTED>; 67 wakeup-source; 68 linux,code = <SW_PEN_INSERTED>; 69 linux,input-type = <EV_SW>; 70 }; 71 }; 72 73 pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&en_pp1800_dpbrdg>; 77 gpios = <&pio 39 GPIO_ACTIVE_HIGH>; 78 regulator-name = "pp1800_dpbrdg_dx"; 79 enable-active-high; 80 vin-supply = <&mt6366_vio18_reg>; 81 }; 82 83 pp3300_disp_x: regulator-pp3300-disp-x { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&edp_panel_fixed_pins>; 87 gpios = <&pio 153 GPIO_ACTIVE_HIGH>; 88 regulator-name = "pp3300_disp_x"; 89 enable-active-high; 90 regulator-boot-on; 91 vin-supply = <&pp3300_z2>; 92 }; 93 94 /* system wide LDO 3.3V power rail */ 95 pp3300_z5: regulator-pp3300-ldo-z5 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_ldo_z5"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 /* separately switched 3.3V power rail */ 106 pp3300_s3: regulator-pp3300-s3 { 107 compatible = "regulator-fixed"; 108 regulator-name = "pp3300_s3"; 109 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 110 regulator-always-on; 111 regulator-boot-on; 112 vin-supply = <&pp3300_z2>; 113 }; 114 115 /* system wide 3.3V power rail */ 116 pp3300_z2: regulator-pp3300-z2 { 117 compatible = "regulator-fixed"; 118 regulator-name = "pp3300_z2"; 119 /* EN pin tied to pp4200_z2, which is controlled by EC */ 120 regulator-always-on; 121 regulator-boot-on; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&ppvar_sys>; 125 }; 126 127 /* system wide 4.2V power rail */ 128 pp4200_z2: regulator-pp4200-z2 { 129 compatible = "regulator-fixed"; 130 regulator-name = "pp4200_z2"; 131 /* controlled by EC */ 132 regulator-always-on; 133 regulator-boot-on; 134 regulator-min-microvolt = <4200000>; 135 regulator-max-microvolt = <4200000>; 136 vin-supply = <&ppvar_sys>; 137 }; 138 139 /* system wide switching 5.0V power rail */ 140 pp5000_z2: regulator-pp5000-z2 { 141 compatible = "regulator-fixed"; 142 regulator-name = "pp5000_z2"; 143 /* controlled by EC */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 vin-supply = <&ppvar_sys>; 149 }; 150 151 /* system wide semi-regulated power rail from battery or USB */ 152 ppvar_sys: regulator-ppvar-sys { 153 compatible = "regulator-fixed"; 154 regulator-name = "ppvar_sys"; 155 regulator-always-on; 156 regulator-boot-on; 157 }; 158 159 reserved_memory: reserved-memory { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 adsp_dma_mem: memory@61000000 { 165 compatible = "shared-dma-pool"; 166 reg = <0 0x61000000 0 0x100000>; 167 no-map; 168 }; 169 170 adsp_mem: memory@60000000 { 171 compatible = "shared-dma-pool"; 172 reg = <0 0x60000000 0 0xA00000>; 173 no-map; 174 }; 175 176 scp_mem: memory@50000000 { 177 compatible = "shared-dma-pool"; 178 reg = <0 0x50000000 0 0x10a0000>; 179 no-map; 180 }; 181 }; 182 183 sound: sound { 184 compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; 185 pinctrl-names = "aud_clk_mosi_off", 186 "aud_clk_mosi_on", 187 "aud_clk_miso_off", 188 "aud_clk_miso_on", 189 "aud_dat_miso_off", 190 "aud_dat_miso_on", 191 "aud_dat_mosi_off", 192 "aud_dat_mosi_on", 193 "aud_gpio_i2s0_off", 194 "aud_gpio_i2s0_on", 195 "aud_gpio_i2s1_off", 196 "aud_gpio_i2s1_on", 197 "aud_gpio_i2s2_off", 198 "aud_gpio_i2s2_on", 199 "aud_gpio_i2s3_off", 200 "aud_gpio_i2s3_on", 201 "aud_gpio_pcm_off", 202 "aud_gpio_pcm_on", 203 "aud_gpio_dmic_sec"; 204 pinctrl-0 = <&aud_clk_mosi_off>; 205 pinctrl-1 = <&aud_clk_mosi_on>; 206 pinctrl-2 = <&aud_clk_miso_off>; 207 pinctrl-3 = <&aud_clk_miso_on>; 208 pinctrl-4 = <&aud_dat_miso_off>; 209 pinctrl-5 = <&aud_dat_miso_on>; 210 pinctrl-6 = <&aud_dat_mosi_off>; 211 pinctrl-7 = <&aud_dat_mosi_on>; 212 pinctrl-8 = <&aud_gpio_i2s0_off>; 213 pinctrl-9 = <&aud_gpio_i2s0_on>; 214 pinctrl-10 = <&aud_gpio_i2s1_off>; 215 pinctrl-11 = <&aud_gpio_i2s1_on>; 216 pinctrl-12 = <&aud_gpio_i2s2_off>; 217 pinctrl-13 = <&aud_gpio_i2s2_on>; 218 pinctrl-14 = <&aud_gpio_i2s3_off>; 219 pinctrl-15 = <&aud_gpio_i2s3_on>; 220 pinctrl-16 = <&aud_gpio_pcm_off>; 221 pinctrl-17 = <&aud_gpio_pcm_on>; 222 pinctrl-18 = <&aud_gpio_dmic_sec>; 223 mediatek,adsp = <&adsp>; 224 mediatek,platform = <&afe>; 225 226 playback-codecs { 227 sound-dai = <&it6505dptx>, <&rt1019p>; 228 }; 229 230 headset-codec { 231 sound-dai = <&rt5682s 0>; 232 }; 233 }; 234 235 rt1019p: speaker-codec { 236 compatible = "realtek,rt1019p"; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&rt1019p_pins_default>; 239 #sound-dai-cells = <0>; 240 sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; 241 }; 242 243 usb_p1_vbus: regulator-usb-p1-vbus { 244 compatible = "regulator-fixed"; 245 gpio = <&pio 148 GPIO_ACTIVE_HIGH>; 246 regulator-name = "vbus1"; 247 regulator-min-microvolt = <5000000>; 248 regulator-max-microvolt = <5000000>; 249 enable-active-high; 250 vin-supply = <&pp5000_z2>; 251 }; 252 253 wifi_pwrseq: wifi-pwrseq { 254 compatible = "mmc-pwrseq-simple"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&wifi_enable_pin>; 257 post-power-on-delay-ms = <50>; 258 reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 259 }; 260 261 wifi_wakeup: wifi-wakeup { 262 compatible = "gpio-keys"; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&wifi_wakeup_pin>; 265 266 wowlan-event { 267 label = "Wake on WiFi"; 268 gpios = <&pio 7 GPIO_ACTIVE_LOW>; 269 linux,code = <KEY_WAKEUP>; 270 wakeup-source; 271 }; 272 }; 273}; 274 275&adsp { 276 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 277 status = "okay"; 278}; 279 280&afe { 281 status = "okay"; 282}; 283 284&cci { 285 proc-supply = <&mt6366_vproc12_reg>; 286}; 287 288&cpu0 { 289 proc-supply = <&mt6366_vproc12_reg>; 290}; 291 292&cpu1 { 293 proc-supply = <&mt6366_vproc12_reg>; 294}; 295 296&cpu2 { 297 proc-supply = <&mt6366_vproc12_reg>; 298}; 299 300&cpu3 { 301 proc-supply = <&mt6366_vproc12_reg>; 302}; 303 304&cpu4 { 305 proc-supply = <&mt6366_vproc12_reg>; 306}; 307 308&cpu5 { 309 proc-supply = <&mt6366_vproc12_reg>; 310}; 311 312&cpu6 { 313 proc-supply = <&mt6366_vproc11_reg>; 314}; 315 316&cpu7 { 317 proc-supply = <&mt6366_vproc11_reg>; 318}; 319 320&dpi { 321 pinctrl-names = "default", "sleep"; 322 pinctrl-0 = <&dpi_pins_default>; 323 pinctrl-1 = <&dpi_pins_sleep>; 324 status = "okay"; 325}; 326 327&dpi_out { 328 remote-endpoint = <&it6505_in>; 329}; 330 331&dsi0 { 332 status = "okay"; 333}; 334 335&gic { 336 mediatek,broken-save-restore-fw; 337}; 338 339&gpu { 340 mali-supply = <&mt6366_vgpu_reg>; 341 status = "okay"; 342}; 343 344&i2c0 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&i2c0_pins>; 347 status = "okay"; 348}; 349 350&i2c1 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&i2c1_pins>; 353 clock-frequency = <400000>; 354 i2c-scl-internal-delay-ns = <8000>; 355 status = "okay"; 356}; 357 358&i2c2 { 359 pinctrl-names = "default"; 360 /* 361 * Trackpad pin put here to work around second source components 362 * sharing the pinmux in steelix designs. 363 */ 364 pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>; 365 clock-frequency = <400000>; 366 i2c-scl-internal-delay-ns = <10000>; 367 status = "okay"; 368 369 trackpad@15 { 370 compatible = "elan,ekth3000"; 371 reg = <0x15>; 372 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; 373 vcc-supply = <&pp3300_s3>; 374 wakeup-source; 375 }; 376}; 377 378&i2c3 { 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c3_pins>; 381 clock-frequency = <100000>; 382 status = "okay"; 383 384 it6505dptx: dp-bridge@5c { 385 compatible = "ite,it6505"; 386 reg = <0x5c>; 387 interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&it6505_pins>; 390 #sound-dai-cells = <0>; 391 ovdd-supply = <&mt6366_vsim2_reg>; 392 pwr18-supply = <&pp1800_dpbrdg_dx>; 393 reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>; 394 395 ports { 396 #address-cells = <1>; 397 #size-cells = <0>; 398 399 port@0 { 400 reg = <0>; 401 402 it6505_in: endpoint { 403 link-frequencies = /bits/ 64 <150000000>; 404 remote-endpoint = <&dpi_out>; 405 }; 406 }; 407 408 port@1 { 409 reg = <1>; 410 }; 411 }; 412 }; 413}; 414 415&i2c5 { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c5_pins>; 418 status = "okay"; 419 420 rt5682s: codec@1a { 421 compatible = "realtek,rt5682s"; 422 reg = <0x1a>; 423 interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; 424 #sound-dai-cells = <1>; 425 AVDD-supply = <&mt6366_vio18_reg>; 426 DBVDD-supply = <&mt6366_vio18_reg>; 427 LDO1-IN-supply = <&mt6366_vio18_reg>; 428 MICVDD-supply = <&pp3300_z2>; 429 realtek,jd-src = <1>; 430 }; 431}; 432 433&mfg0 { 434 domain-supply = <&mt6366_vsram_gpu_reg>; 435}; 436 437&mfg1 { 438 domain-supply = <&mt6366_vgpu_reg>; 439}; 440 441&mipi_tx0 { 442 status = "okay"; 443}; 444 445&mmc0 { 446 pinctrl-names = "default", "state_uhs"; 447 pinctrl-0 = <&mmc0_pins_default>; 448 pinctrl-1 = <&mmc0_pins_uhs>; 449 bus-width = <8>; 450 max-frequency = <200000000>; 451 non-removable; 452 cap-mmc-highspeed; 453 mmc-hs200-1_8v; 454 mmc-hs400-1_8v; 455 supports-cqe; 456 no-sd; 457 no-sdio; 458 cap-mmc-hw-reset; 459 hs400-ds-delay = <0x11814>; 460 mediatek,hs400-ds-dly3 = <0x14>; 461 vmmc-supply = <&mt6366_vemc_reg>; 462 vqmmc-supply = <&mt6366_vio18_reg>; 463 status = "okay"; 464}; 465 466&mmc1 { 467 pinctrl-names = "default", "state_uhs", "state_eint"; 468 pinctrl-0 = <&mmc1_pins_default>; 469 pinctrl-1 = <&mmc1_pins_uhs>; 470 pinctrl-2 = <&mmc1_pins_eint>; 471 /delete-property/ interrupts; 472 interrupt-names = "msdc", "sdio_wakeup"; 473 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 474 <&pio 87 IRQ_TYPE_LEVEL_LOW>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 bus-width = <4>; 478 max-frequency = <200000000>; 479 cap-sd-highspeed; 480 sd-uhs-sdr104; 481 sd-uhs-sdr50; 482 keep-power-in-suspend; 483 wakeup-source; 484 cap-sdio-irq; 485 no-mmc; 486 no-sd; 487 non-removable; 488 vmmc-supply = <&pp3300_s3>; 489 vqmmc-supply = <&mt6366_vio18_reg>; 490 mmc-pwrseq = <&wifi_pwrseq>; 491 status = "okay"; 492 493 bluetooth@2 { 494 compatible = "mediatek,mt7921s-bluetooth"; 495 reg = <2>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&bt_pins_reset>; 498 reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; 499 }; 500}; 501 502&nor_flash { 503 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&nor_pins_default>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "okay"; 509 510 flash@0 { 511 compatible = "jedec,spi-nor"; 512 reg = <0>; 513 spi-max-frequency = <39000000>; 514 }; 515}; 516 517&pio { 518 /* 185 lines */ 519 gpio-line-names = "TP", 520 "TP", 521 "TP", 522 "I2S0_HP_DI", 523 "I2S3_DP_SPKR_DO", 524 "SAR_INT_ODL", 525 "BT_WAKE_AP_ODL", 526 "WIFI_INT_ODL", 527 "DPBRDG_INT_ODL", 528 "EDPBRDG_INT_ODL", 529 "EC_AP_HPD_OD", 530 "TCHPAD_INT_ODL", 531 "TCHSCR_INT_1V8_ODL", 532 "EC_AP_INT_ODL", 533 "EC_IN_RW_ODL", 534 "GSC_AP_INT_ODL", 535 /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 536 "AP_FLASH_WP_L", 537 "HP_INT_ODL", 538 "PEN_EJECT_OD", 539 "WCAM_PWDN_L", 540 "WCAM_RST_L", 541 "UCAM_SEN_EN", 542 "UCAM_RST_L", 543 "LTE_RESET_L", 544 "LTE_SAR_DETECT_L", 545 "I2S2_DP_SPK_MCK", 546 "I2S2_DP_SPKR_BCK", 547 "I2S2_DP_SPKR_LRCK", 548 "I2S2_DP_SPKR_DI (TP)", 549 "EN_PP1000_EDPBRDG", 550 "EN_PP1800_EDPBRDG", 551 "EN_PP3300_EDPBRDG", 552 "UART_GSC_TX_AP_RX", 553 "UART_AP_TX_GSC_RX", 554 "UART_DBGCON_TX_ADSP_RX", 555 "UART_ADSP_TX_DBGCON_RX", 556 "EN_PP1000_DPBRDG", 557 "TCHSCR_REPORT_DISABLE", 558 "EN_PP3300_DPBRDG", 559 "EN_PP1800_DPBRDG", 560 "SPI_AP_CLK_EC", 561 "SPI_AP_CS_EC_L", 562 "SPI_AP_DO_EC_DI", 563 "SPI_AP_DI_EC_DO", 564 "SPI_AP_CLK_GSC", 565 "SPI_AP_CS_GSC_L", 566 "SPI_AP_DO_GSC_DI", 567 "SPI_AP_DI_GSC_DO", 568 "UART_DBGCON_TX_SCP_RX", 569 "UART_SCP_TX_DBGCON_RX", 570 "EN_PP1200_CAM_X", 571 "EN_PP2800A_VCM_X", 572 "EN_PP2800A_UCAM_X", 573 "EN_PP2800A_WCAM_X", 574 "WLAN_MODULE_RST_L", 575 "EN_PP1200_UCAM_X", 576 "I2S1_HP_DO", 577 "I2S1_HP_BCK", 578 "I2S1_HP_LRCK", 579 "I2S1_HP_MCK", 580 "TCHSCR_RST_1V8_L", 581 "SPI_AP_CLK_ROM", 582 "SPI_AP_CS_ROM_L", 583 "SPI_AP_DO_ROM_DI", 584 "SPI_AP_DI_ROM_DO", 585 "NC", 586 "NC", 587 "EMMC_STRB", 588 "EMMC_CLK", 589 "EMMC_CMD", 590 "EMMC_RST_L", 591 "EMMC_DATA0", 592 "EMMC_DATA1", 593 "EMMC_DATA2", 594 "EMMC_DATA3", 595 "EMMC_DATA4", 596 "EMMC_DATA5", 597 "EMMC_DATA6", 598 "EMMC_DATA7", 599 "AP_KPCOL0", 600 "NC", 601 "NC", 602 "NC", 603 "TP", 604 "SDIO_CLK", 605 "SDIO_CMD", 606 "SDIO_DATA0", 607 "SDIO_DATA1", 608 "SDIO_DATA2", 609 "SDIO_DATA3", 610 "NC", 611 "NC", 612 "NC", 613 "NC", 614 "NC", 615 "NC", 616 "EDPBRDG_PWREN", 617 "BL_PWM_1V8", 618 "EDPBRDG_RST_L", 619 "MIPI_DPI_CLK", 620 "MIPI_DPI_VSYNC", 621 "MIPI_DPI_HSYNC", 622 "MIPI_DPI_DE", 623 "MIPI_DPI_D0", 624 "MIPI_DPI_D1", 625 "MIPI_DPI_D2", 626 "MIPI_DPI_D3", 627 "MIPI_DPI_D4", 628 "MIPI_DPI_D5", 629 "MIPI_DPI_D6", 630 "MIPI_DPI_DA7", 631 "MIPI_DPI_D8", 632 "MIPI_DPI_D9", 633 "MIPI_DPI_D10", 634 "MIPI_DPI_D11", 635 "PCM_BT_CLK", 636 "PCM_BT_SYNC", 637 "PCM_BT_DI", 638 "PCM_BT_DO", 639 "JTAG_TMS_TP", 640 "JTAG_TCK_TP", 641 "JTAG_TDI_TP", 642 "JTAG_TDO_TP", 643 "JTAG_TRSTN_TP", 644 "CLK_24M_WCAM", 645 "CLK_24M_UCAM", 646 "UCAM_DET_ODL", 647 "AP_I2C_EDPBRDG_SCL_1V8", 648 "AP_I2C_EDPBRDG_SDA_1V8", 649 "AP_I2C_TCHSCR_SCL_1V8", 650 "AP_I2C_TCHSCR_SDA_1V8", 651 "AP_I2C_TCHPAD_SCL_1V8", 652 "AP_I2C_TCHPAD_SDA_1V8", 653 "AP_I2C_DPBRDG_SCL_1V8", 654 "AP_I2C_DPBRDG_SDA_1V8", 655 "AP_I2C_WLAN_SCL_1V8", 656 "AP_I2C_WLAN_SDA_1V8", 657 "AP_I2C_AUD_SCL_1V8", 658 "AP_I2C_AUD_SDA_1V8", 659 "AP_I2C_TPM_SCL_1V8", 660 "AP_I2C_UCAM_SDA_1V8", 661 "AP_I2C_UCAM_SCL_1V8", 662 "AP_I2C_UCAM_SDA_1V8", 663 "AP_I2C_WCAM_SCL_1V8", 664 "AP_I2C_WCAM_SDA_1V8", 665 "SCP_I2C_SENSOR_SCL_1V8", 666 "SCP_I2C_SENSOR_SDA_1V8", 667 "AP_EC_WARM_RST_REQ", 668 "AP_XHCI_INIT_DONE", 669 "USB3_HUB_RST_L", 670 "EN_SPKR", 671 "BEEP_ON", 672 "AP_EDP_BKLTEN", 673 "EN_PP3300_DISP_X", 674 "EN_PP3300_SDBRDG_X", 675 "BT_KILL_1V8_L", 676 "WIFI_KILL_1V8_L", 677 "PWRAP_SPI0_CSN", 678 "PWRAP_SPI0_CK", 679 "PWRAP_SPI0_MO", 680 "PWRAP_SPI0_MI", 681 "SRCLKENA0", 682 "SRCLKENA1", 683 "SCP_VREQ_VAO", 684 "AP_RTC_CLK32K", 685 "AP_PMIC_WDTRST_L", 686 "AUD_CLK_MOSI", 687 "AUD_SYNC_MOSI", 688 "AUD_DAT_MOSI0", 689 "AUD_DAT_MOSI1", 690 "AUD_CLK_MISO", 691 "AUD_SYNC_MISO", 692 "AUD_DAT_MISO0", 693 "AUD_DAT_MISO1", 694 "NC", 695 "NC", 696 "DPBRDG_PWREN", 697 "DPBRDG_RST_L", 698 "LTE_W_DISABLE_L", 699 "LTE_SAR_DETECT_L", 700 "EN_PP3300_LTE_X", 701 "LTE_PWR_OFF_L", 702 "LTE_RESET_L", 703 "TP", 704 "TP"; 705 706 aud_clk_mosi_off: aud-clk-mosi-off-pins { 707 pins-clk-sync { 708 pinmux = <PINMUX_GPIO166__FUNC_GPIO166>, 709 <PINMUX_GPIO167__FUNC_GPIO167>; 710 input-enable; 711 bias-pull-down; 712 }; 713 }; 714 715 aud_clk_mosi_on: aud-clk-mosi-on-pins { 716 pins-clk-sync { 717 pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>, 718 <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>; 719 }; 720 }; 721 722 aud_clk_miso_off: aud-clk-miso-off-pins { 723 pins-clk-sync { 724 pinmux = <PINMUX_GPIO170__FUNC_GPIO170>, 725 <PINMUX_GPIO171__FUNC_GPIO171>; 726 input-enable; 727 bias-pull-down; 728 }; 729 }; 730 731 aud_clk_miso_on: aud-clk-miso-on-pins { 732 pins-clk-sync { 733 pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>, 734 <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>; 735 }; 736 }; 737 738 aud_dat_mosi_off: aud-dat-mosi-off-pins { 739 pins-dat { 740 pinmux = <PINMUX_GPIO168__FUNC_GPIO168>, 741 <PINMUX_GPIO169__FUNC_GPIO169>; 742 input-enable; 743 bias-pull-down; 744 }; 745 }; 746 747 aud_dat_mosi_on: aud-dat-mosi-on-pins { 748 pins-dat { 749 pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>, 750 <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>; 751 }; 752 }; 753 754 aud_dat_miso_off: aud-dat-miso-off-pins { 755 pins-dat { 756 pinmux = <PINMUX_GPIO172__FUNC_GPIO172>, 757 <PINMUX_GPIO173__FUNC_GPIO173>; 758 input-enable; 759 bias-pull-down; 760 }; 761 }; 762 763 aud_dat_miso_on: aud-dat-miso-on-pins { 764 pins-dat { 765 pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>, 766 <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>; 767 input-schmitt-enable; 768 bias-disable; 769 }; 770 }; 771 772 aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { 773 pins-sdata { 774 pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; 775 }; 776 }; 777 778 aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { 779 pins-sdata { 780 pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>; 781 }; 782 }; 783 784 aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { 785 pins-clk-sdata { 786 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>, 787 <PINMUX_GPIO57__FUNC_GPIO57>, 788 <PINMUX_GPIO58__FUNC_GPIO58>, 789 <PINMUX_GPIO59__FUNC_GPIO59>; 790 output-low; 791 }; 792 }; 793 794 aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { 795 pins-clk-sdata { 796 pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>, 797 <PINMUX_GPIO57__FUNC_I2S1_BCK>, 798 <PINMUX_GPIO58__FUNC_I2S1_LRCK>, 799 <PINMUX_GPIO59__FUNC_I2S1_MCK>; 800 }; 801 }; 802 803 aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { 804 pins-cmd-dat { 805 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>, 806 <PINMUX_GPIO27__FUNC_GPIO27>; 807 output-low; 808 }; 809 }; 810 811 aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { 812 pins-clk { 813 pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>, 814 <PINMUX_GPIO27__FUNC_I2S2_LRCK>; 815 drive-strength = <4>; 816 }; 817 }; 818 819 aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { 820 pins-sdata { 821 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 822 output-low; 823 }; 824 }; 825 826 aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { 827 pins-sdata { 828 pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>; 829 drive-strength = <4>; 830 }; 831 }; 832 833 aud_gpio_pcm_off: aud-gpio-pcm-off-pins { 834 pins-clk-sdata { 835 pinmux = <PINMUX_GPIO115__FUNC_GPIO115>, 836 <PINMUX_GPIO116__FUNC_GPIO116>, 837 <PINMUX_GPIO117__FUNC_GPIO117>, 838 <PINMUX_GPIO118__FUNC_GPIO118>; 839 output-low; 840 }; 841 }; 842 843 aud_gpio_pcm_on: aud-gpio-pcm-on-pins { 844 pins-clk-sdata { 845 pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>, 846 <PINMUX_GPIO116__FUNC_PCM_SYNC>, 847 <PINMUX_GPIO117__FUNC_PCM_DI>, 848 <PINMUX_GPIO118__FUNC_PCM_DO>; 849 }; 850 }; 851 852 aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { 853 pins { 854 pinmux = <PINMUX_GPIO23__FUNC_GPIO23>; 855 output-low; 856 }; 857 }; 858 859 bt_pins_reset: bt-reset-pins { 860 pins-bt-reset { 861 pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; 862 output-high; 863 }; 864 }; 865 866 dpi_pins_sleep: dpi-sleep-pins { 867 pins-cmd-dat { 868 pinmux = <PINMUX_GPIO103__FUNC_GPIO103>, 869 <PINMUX_GPIO104__FUNC_GPIO104>, 870 <PINMUX_GPIO105__FUNC_GPIO105>, 871 <PINMUX_GPIO106__FUNC_GPIO106>, 872 <PINMUX_GPIO107__FUNC_GPIO107>, 873 <PINMUX_GPIO108__FUNC_GPIO108>, 874 <PINMUX_GPIO109__FUNC_GPIO109>, 875 <PINMUX_GPIO110__FUNC_GPIO110>, 876 <PINMUX_GPIO111__FUNC_GPIO111>, 877 <PINMUX_GPIO112__FUNC_GPIO112>, 878 <PINMUX_GPIO113__FUNC_GPIO113>, 879 <PINMUX_GPIO114__FUNC_GPIO114>, 880 <PINMUX_GPIO101__FUNC_GPIO101>, 881 <PINMUX_GPIO100__FUNC_GPIO100>, 882 <PINMUX_GPIO102__FUNC_GPIO102>, 883 <PINMUX_GPIO99__FUNC_GPIO99>; 884 drive-strength = <10>; 885 output-low; 886 }; 887 }; 888 889 dpi_pins_default: dpi-default-pins { 890 pins-cmd-dat { 891 pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>, 892 <PINMUX_GPIO104__FUNC_DPI_DATA1>, 893 <PINMUX_GPIO105__FUNC_DPI_DATA2>, 894 <PINMUX_GPIO106__FUNC_DPI_DATA3>, 895 <PINMUX_GPIO107__FUNC_DPI_DATA4>, 896 <PINMUX_GPIO108__FUNC_DPI_DATA5>, 897 <PINMUX_GPIO109__FUNC_DPI_DATA6>, 898 <PINMUX_GPIO110__FUNC_DPI_DATA7>, 899 <PINMUX_GPIO111__FUNC_DPI_DATA8>, 900 <PINMUX_GPIO112__FUNC_DPI_DATA9>, 901 <PINMUX_GPIO113__FUNC_DPI_DATA10>, 902 <PINMUX_GPIO114__FUNC_DPI_DATA11>, 903 <PINMUX_GPIO101__FUNC_DPI_HSYNC>, 904 <PINMUX_GPIO100__FUNC_DPI_VSYNC>, 905 <PINMUX_GPIO102__FUNC_DPI_DE>, 906 <PINMUX_GPIO99__FUNC_DPI_PCLK>; 907 drive-strength = <10>; 908 }; 909 }; 910 911 ec_ap_int: cros-ec-int-pins { 912 pins-ec-ap-int-odl { 913 pinmux = <PINMUX_GPIO13__FUNC_GPIO13>; 914 input-enable; 915 }; 916 }; 917 918 edp_panel_fixed_pins: edp-panel-fixed-pins { 919 pins-vreg-en { 920 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 921 output-high; 922 }; 923 }; 924 925 en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { 926 pins-vreg-en { 927 pinmux = <PINMUX_GPIO39__FUNC_GPIO39>; 928 output-low; 929 }; 930 }; 931 932 gsc_int: gsc-int-pins { 933 pins-gsc-ap-int-odl { 934 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 935 input-enable; 936 }; 937 }; 938 939 i2c0_pins: i2c0-pins { 940 pins-bus { 941 pinmux = <PINMUX_GPIO128__FUNC_SDA0>, 942 <PINMUX_GPIO127__FUNC_SCL0>; 943 bias-disable; 944 drive-strength = <4>; 945 input-enable; 946 }; 947 }; 948 949 i2c1_pins: i2c1-pins { 950 pins-bus { 951 pinmux = <PINMUX_GPIO130__FUNC_SDA1>, 952 <PINMUX_GPIO129__FUNC_SCL1>; 953 bias-disable; 954 drive-strength = <4>; 955 input-enable; 956 }; 957 }; 958 959 i2c2_pins: i2c2-pins { 960 pins-bus { 961 pinmux = <PINMUX_GPIO132__FUNC_SDA2>, 962 <PINMUX_GPIO131__FUNC_SCL2>; 963 bias-disable; 964 drive-strength = <4>; 965 input-enable; 966 }; 967 }; 968 969 i2c3_pins: i2c3-pins { 970 pins-bus { 971 pinmux = <PINMUX_GPIO134__FUNC_SDA3>, 972 <PINMUX_GPIO133__FUNC_SCL3>; 973 bias-disable; 974 drive-strength = <4>; 975 input-enable; 976 }; 977 }; 978 979 i2c5_pins: i2c5-pins { 980 pins-bus { 981 pinmux = <PINMUX_GPIO138__FUNC_SDA5>, 982 <PINMUX_GPIO137__FUNC_SCL5>; 983 bias-disable; 984 drive-strength = <4>; 985 input-enable; 986 }; 987 }; 988 989 it6505_pins: it6505-pins { 990 pins-hpd { 991 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>; 992 input-enable; 993 bias-pull-up; 994 }; 995 996 pins-int { 997 pinmux = <PINMUX_GPIO8__FUNC_GPIO8>; 998 input-enable; 999 bias-pull-up; 1000 }; 1001 1002 pins-reset { 1003 pinmux = <PINMUX_GPIO177__FUNC_GPIO177>; 1004 output-low; 1005 bias-pull-up; 1006 }; 1007 }; 1008 1009 mmc0_pins_default: mmc0-default-pins { 1010 pins-clk { 1011 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1012 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1013 }; 1014 1015 pins-cmd-dat { 1016 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1017 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1018 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1019 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1020 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1021 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1022 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1023 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1024 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1025 input-enable; 1026 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1027 }; 1028 1029 pins-rst { 1030 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1031 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1032 }; 1033 }; 1034 1035 mmc0_pins_uhs: mmc0-uhs-pins { 1036 pins-clk { 1037 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1038 drive-strength = <6>; 1039 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1040 }; 1041 1042 pins-cmd-dat { 1043 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1044 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1045 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1046 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1047 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1048 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1049 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1050 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1051 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1052 input-enable; 1053 drive-strength = <6>; 1054 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1055 }; 1056 1057 pins-ds { 1058 pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>; 1059 drive-strength = <6>; 1060 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1061 }; 1062 1063 pins-rst { 1064 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1065 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1066 }; 1067 }; 1068 1069 mmc1_pins_default: mmc1-default-pins { 1070 pins-clk { 1071 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1072 drive-strength = <6>; 1073 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1074 }; 1075 1076 pins-cmd-dat { 1077 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1078 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1079 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1080 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1081 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1082 input-enable; 1083 drive-strength = <6>; 1084 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1085 }; 1086 }; 1087 1088 mmc1_pins_uhs: mmc1-uhs-pins { 1089 pins-clk { 1090 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1091 drive-strength = <6>; 1092 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1093 }; 1094 1095 pins-cmd-dat { 1096 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1097 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1098 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1099 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1100 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1101 input-enable; 1102 drive-strength = <8>; 1103 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1104 }; 1105 }; 1106 1107 mmc1_pins_eint: mmc1-eint-pins { 1108 pins-dat1 { 1109 pinmux = <PINMUX_GPIO87__FUNC_GPIO87>; 1110 input-enable; 1111 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1112 }; 1113 }; 1114 1115 nor_pins_default: nor-default-pins { 1116 pins-clk-dat { 1117 pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>, 1118 <PINMUX_GPIO61__FUNC_SPINOR_CK>, 1119 <PINMUX_GPIO64__FUNC_SPINOR_IO1>; 1120 drive-strength = <6>; 1121 bias-pull-down; 1122 }; 1123 1124 pins-cs-dat { 1125 pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>, 1126 <PINMUX_GPIO65__FUNC_SPINOR_IO2>, 1127 <PINMUX_GPIO66__FUNC_SPINOR_IO3>; 1128 drive-strength = <6>; 1129 bias-pull-up; 1130 }; 1131 }; 1132 1133 pen_eject: pen-eject-pins { 1134 pins { 1135 pinmux = <PINMUX_GPIO18__FUNC_GPIO18>; 1136 input-enable; 1137 /* External pull-up. */ 1138 bias-disable; 1139 }; 1140 }; 1141 1142 pwm0_pin: disp-pwm-pins { 1143 pins { 1144 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>; 1145 output-high; 1146 }; 1147 }; 1148 1149 rt1019p_pins_default: rt1019p-default-pins { 1150 pins-sdb { 1151 pinmux = <PINMUX_GPIO150__FUNC_GPIO150>; 1152 output-low; 1153 }; 1154 }; 1155 1156 scp_pins: scp-default-pins { 1157 pins-scp-uart { 1158 pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>, 1159 <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>; 1160 }; 1161 }; 1162 1163 spi1_pins: spi1-pins { 1164 pins-bus { 1165 pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>, 1166 <PINMUX_GPIO41__FUNC_SPI1_CSB_A>, 1167 <PINMUX_GPIO42__FUNC_SPI1_MO_A>, 1168 <PINMUX_GPIO43__FUNC_SPI1_MI_A>; 1169 bias-disable; 1170 input-enable; 1171 }; 1172 }; 1173 1174 spi2_pins: spi2-pins { 1175 pins-bus { 1176 pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>, 1177 <PINMUX_GPIO45__FUNC_GPIO45>, 1178 <PINMUX_GPIO46__FUNC_SPI2_MO_A>, 1179 <PINMUX_GPIO47__FUNC_SPI2_MI_A>; 1180 bias-disable; 1181 input-enable; 1182 }; 1183 }; 1184 1185 spmi_pins: spmi-pins { 1186 pins-bus { 1187 pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>, 1188 <PINMUX_GPIO184__FUNC_SPMI_SDA>; 1189 }; 1190 }; 1191 1192 touchscreen_pins: touchscreen-pins { 1193 pins-irq { 1194 pinmux = <PINMUX_GPIO12__FUNC_GPIO12>; 1195 input-enable; 1196 bias-pull-up; 1197 }; 1198 1199 pins-reset { 1200 pinmux = <PINMUX_GPIO60__FUNC_GPIO60>; 1201 output-high; 1202 }; 1203 1204 pins-report-sw { 1205 pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; 1206 output-low; 1207 }; 1208 }; 1209 1210 trackpad_pin: trackpad-default-pins { 1211 pins-int-n { 1212 pinmux = <PINMUX_GPIO11__FUNC_GPIO11>; 1213 input-enable; 1214 bias-disable; /* pulled externally */ 1215 }; 1216 }; 1217 1218 wifi_enable_pin: wifi-enable-pins { 1219 pins-wifi-enable { 1220 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1221 }; 1222 }; 1223 1224 wifi_wakeup_pin: wifi-wakeup-pins { 1225 pins-wifi-wakeup { 1226 pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; 1227 input-enable; 1228 }; 1229 }; 1230}; 1231 1232&pwm0 { 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&pwm0_pin>; 1235 status = "okay"; 1236}; 1237 1238&pwrap { 1239 pmic { 1240 compatible = "mediatek,mt6366", "mediatek,mt6358"; 1241 interrupt-controller; 1242 interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; 1243 #interrupt-cells = <2>; 1244 1245 mt6366codec: codec { 1246 compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; 1247 Avdd-supply = <&mt6366_vaud28_reg>; 1248 mediatek,dmic-mode = <1>; /* one-wire */ 1249 }; 1250 1251 mt6366_regulators: regulators { 1252 compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; 1253 vsys-ldo1-supply = <&pp4200_z2>; 1254 vsys-ldo2-supply = <&pp4200_z2>; 1255 vsys-ldo3-supply = <&pp4200_z2>; 1256 vsys-vcore-supply = <&pp4200_z2>; 1257 vsys-vdram1-supply = <&pp4200_z2>; 1258 vsys-vgpu-supply = <&pp4200_z2>; 1259 vsys-vmodem-supply = <&pp4200_z2>; 1260 vsys-vpa-supply = <&pp4200_z2>; 1261 vsys-vproc11-supply = <&pp4200_z2>; 1262 vsys-vproc12-supply = <&pp4200_z2>; 1263 vsys-vs1-supply = <&pp4200_z2>; 1264 vsys-vs2-supply = <&pp4200_z2>; 1265 vs1-ldo1-supply = <&mt6366_vs1_reg>; 1266 vs2-ldo1-supply = <&mt6366_vdram1_reg>; 1267 vs2-ldo2-supply = <&mt6366_vs2_reg>; 1268 vs2-ldo3-supply = <&mt6366_vs2_reg>; 1269 1270 vcore { 1271 regulator-name = "pp0750_dvdd_core"; 1272 regulator-min-microvolt = <550000>; 1273 regulator-max-microvolt = <800000>; 1274 regulator-ramp-delay = <6250>; 1275 regulator-enable-ramp-delay = <200>; 1276 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1277 MT6397_BUCK_MODE_FORCE_PWM>; 1278 regulator-always-on; 1279 }; 1280 1281 mt6366_vdram1_reg: vdram1 { 1282 regulator-name = "pp1125_emi_vdd2"; 1283 regulator-min-microvolt = <1125000>; 1284 regulator-max-microvolt = <1125000>; 1285 regulator-ramp-delay = <12500>; 1286 regulator-enable-ramp-delay = <0>; 1287 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1288 MT6397_BUCK_MODE_FORCE_PWM>; 1289 regulator-always-on; 1290 }; 1291 1292 mt6366_vgpu_reg: vgpu { 1293 /* 1294 * Called "ppvar_dvdd_gpu" in the schematic. 1295 * Called "ppvar_dvdd_vgpu" here to match 1296 * regulator coupling requirements. 1297 */ 1298 regulator-name = "ppvar_dvdd_vgpu"; 1299 regulator-min-microvolt = <500000>; 1300 regulator-max-microvolt = <950000>; 1301 regulator-ramp-delay = <6250>; 1302 regulator-enable-ramp-delay = <200>; 1303 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1304 MT6397_BUCK_MODE_FORCE_PWM>; 1305 regulator-coupled-with = <&mt6366_vsram_gpu_reg>; 1306 regulator-coupled-max-spread = <10000>; 1307 }; 1308 1309 mt6366_vproc11_reg: vproc11 { 1310 regulator-name = "ppvar_dvdd_proc_bc_mt6366"; 1311 regulator-min-microvolt = <600000>; 1312 regulator-max-microvolt = <1200000>; 1313 regulator-ramp-delay = <6250>; 1314 regulator-enable-ramp-delay = <200>; 1315 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1316 MT6397_BUCK_MODE_FORCE_PWM>; 1317 regulator-always-on; 1318 }; 1319 1320 mt6366_vproc12_reg: vproc12 { 1321 regulator-name = "ppvar_dvdd_proc_lc"; 1322 regulator-min-microvolt = <600000>; 1323 regulator-max-microvolt = <1200000>; 1324 regulator-ramp-delay = <6250>; 1325 regulator-enable-ramp-delay = <200>; 1326 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1327 MT6397_BUCK_MODE_FORCE_PWM>; 1328 regulator-always-on; 1329 }; 1330 1331 mt6366_vs1_reg: vs1 { 1332 regulator-name = "pp2000_vs1"; 1333 regulator-min-microvolt = <2000000>; 1334 regulator-max-microvolt = <2000000>; 1335 regulator-ramp-delay = <12500>; 1336 regulator-enable-ramp-delay = <0>; 1337 regulator-always-on; 1338 }; 1339 1340 mt6366_vs2_reg: vs2 { 1341 regulator-name = "pp1350_vs2"; 1342 regulator-min-microvolt = <1350000>; 1343 regulator-max-microvolt = <1350000>; 1344 regulator-ramp-delay = <12500>; 1345 regulator-enable-ramp-delay = <0>; 1346 regulator-always-on; 1347 }; 1348 1349 va12 { 1350 regulator-name = "pp1200_va12"; 1351 regulator-min-microvolt = <1200000>; 1352 regulator-max-microvolt = <1200000>; 1353 regulator-enable-ramp-delay = <270>; 1354 regulator-always-on; 1355 }; 1356 1357 mt6366_vaud28_reg: vaud28 { 1358 regulator-name = "pp2800_vaud28"; 1359 regulator-min-microvolt = <2800000>; 1360 regulator-max-microvolt = <2800000>; 1361 regulator-enable-ramp-delay = <270>; 1362 }; 1363 1364 mt6366_vaux18_reg: vaux18 { 1365 regulator-name = "pp1840_vaux18"; 1366 regulator-min-microvolt = <1800000>; 1367 regulator-max-microvolt = <1840000>; 1368 regulator-enable-ramp-delay = <270>; 1369 }; 1370 1371 mt6366_vbif28_reg: vbif28 { 1372 regulator-name = "pp2800_vbif28"; 1373 regulator-min-microvolt = <2800000>; 1374 regulator-max-microvolt = <2800000>; 1375 regulator-enable-ramp-delay = <270>; 1376 }; 1377 1378 mt6366_vcn18_reg: vcn18 { 1379 regulator-name = "pp1800_vcn18_x"; 1380 regulator-min-microvolt = <1800000>; 1381 regulator-max-microvolt = <1800000>; 1382 regulator-enable-ramp-delay = <270>; 1383 }; 1384 1385 mt6366_vcn28_reg: vcn28 { 1386 regulator-name = "pp2800_vcn28_x"; 1387 regulator-min-microvolt = <2800000>; 1388 regulator-max-microvolt = <2800000>; 1389 regulator-enable-ramp-delay = <270>; 1390 }; 1391 1392 mt6366_vefuse_reg: vefuse { 1393 regulator-name = "pp1800_vefuse"; 1394 regulator-min-microvolt = <1800000>; 1395 regulator-max-microvolt = <1800000>; 1396 regulator-enable-ramp-delay = <270>; 1397 }; 1398 1399 mt6366_vfe28_reg: vfe28 { 1400 regulator-name = "pp2800_vfe28_x"; 1401 regulator-min-microvolt = <2800000>; 1402 regulator-max-microvolt = <2800000>; 1403 regulator-enable-ramp-delay = <270>; 1404 }; 1405 1406 mt6366_vemc_reg: vemc { 1407 regulator-name = "pp3000_vemc"; 1408 regulator-min-microvolt = <3000000>; 1409 regulator-max-microvolt = <3000000>; 1410 regulator-enable-ramp-delay = <60>; 1411 }; 1412 1413 mt6366_vibr_reg: vibr { 1414 regulator-name = "pp2800_vibr_x"; 1415 regulator-min-microvolt = <2800000>; 1416 regulator-max-microvolt = <2800000>; 1417 regulator-enable-ramp-delay = <60>; 1418 }; 1419 1420 mt6366_vio18_reg: vio18 { 1421 regulator-name = "pp1800_vio18_s3"; 1422 regulator-min-microvolt = <1800000>; 1423 regulator-max-microvolt = <1800000>; 1424 regulator-enable-ramp-delay = <2700>; 1425 regulator-always-on; 1426 }; 1427 1428 mt6366_vio28_reg: vio28 { 1429 regulator-name = "pp2800_vio28_x"; 1430 regulator-min-microvolt = <2800000>; 1431 regulator-max-microvolt = <2800000>; 1432 regulator-enable-ramp-delay = <270>; 1433 }; 1434 1435 mt6366_vm18_reg: vm18 { 1436 regulator-name = "pp1800_emi_vdd1"; 1437 regulator-min-microvolt = <1800000>; 1438 regulator-max-microvolt = <1840000>; 1439 regulator-enable-ramp-delay = <325>; 1440 regulator-always-on; 1441 }; 1442 1443 mt6366_vmc_reg: vmc { 1444 regulator-name = "pp3000_vmc"; 1445 regulator-min-microvolt = <3000000>; 1446 regulator-max-microvolt = <3000000>; 1447 regulator-enable-ramp-delay = <60>; 1448 }; 1449 1450 mt6366_vmddr_reg: vmddr { 1451 regulator-name = "pm0750_emi_vmddr"; 1452 regulator-min-microvolt = <700000>; 1453 regulator-max-microvolt = <750000>; 1454 regulator-enable-ramp-delay = <325>; 1455 regulator-always-on; 1456 }; 1457 1458 mt6366_vmch_reg: vmch { 1459 regulator-name = "pp3000_vmch"; 1460 regulator-min-microvolt = <3000000>; 1461 regulator-max-microvolt = <3000000>; 1462 regulator-enable-ramp-delay = <60>; 1463 }; 1464 1465 mt6366_vcn33_reg: vcn33 { 1466 regulator-name = "pp3300_vcn33_x"; 1467 regulator-min-microvolt = <3300000>; 1468 regulator-max-microvolt = <3300000>; 1469 regulator-enable-ramp-delay = <270>; 1470 }; 1471 1472 vdram2 { 1473 regulator-name = "pp0600_emi_vddq"; 1474 regulator-min-microvolt = <600000>; 1475 regulator-max-microvolt = <600000>; 1476 regulator-enable-ramp-delay = <3300>; 1477 regulator-always-on; 1478 }; 1479 1480 mt6366_vrf12_reg: vrf12 { 1481 regulator-name = "pp1200_vrf12_x"; 1482 regulator-min-microvolt = <1200000>; 1483 regulator-max-microvolt = <1200000>; 1484 regulator-enable-ramp-delay = <120>; 1485 }; 1486 1487 mt6366_vrf18_reg: vrf18 { 1488 regulator-name = "pp1800_vrf18_x"; 1489 regulator-min-microvolt = <1800000>; 1490 regulator-max-microvolt = <1800000>; 1491 regulator-enable-ramp-delay = <120>; 1492 }; 1493 1494 vsim1 { 1495 regulator-name = "pp1860_vsim1_x"; 1496 regulator-min-microvolt = <1800000>; 1497 regulator-max-microvolt = <1860000>; 1498 regulator-enable-ramp-delay = <540>; 1499 }; 1500 1501 mt6366_vsim2_reg: vsim2 { 1502 regulator-name = "pp2760_vsim2_x"; 1503 regulator-min-microvolt = <2700000>; 1504 regulator-max-microvolt = <2760000>; 1505 regulator-enable-ramp-delay = <540>; 1506 }; 1507 1508 mt6366_vsram_gpu_reg: vsram-gpu { 1509 regulator-name = "pp0900_dvdd_sram_gpu"; 1510 regulator-min-microvolt = <850000>; 1511 regulator-max-microvolt = <1050000>; 1512 regulator-ramp-delay = <6250>; 1513 regulator-enable-ramp-delay = <240>; 1514 regulator-coupled-with = <&mt6366_vgpu_reg>; 1515 regulator-coupled-max-spread = <10000>; 1516 }; 1517 1518 mt6366_vsram_others_reg: vsram-others { 1519 regulator-name = "pp0900_dvdd_sram_core"; 1520 regulator-min-microvolt = <900000>; 1521 regulator-max-microvolt = <900000>; 1522 regulator-ramp-delay = <6250>; 1523 regulator-enable-ramp-delay = <240>; 1524 regulator-always-on; 1525 }; 1526 1527 mt6366_vsram_proc11_reg: vsram-proc11 { 1528 regulator-name = "pp0900_dvdd_sram_bc"; 1529 regulator-min-microvolt = <850000>; 1530 regulator-max-microvolt = <1120000>; 1531 regulator-ramp-delay = <6250>; 1532 regulator-enable-ramp-delay = <240>; 1533 regulator-always-on; 1534 }; 1535 1536 mt6366_vsram_proc12_reg: vsram-proc12 { 1537 regulator-name = "pp0900_dvdd_sram_lc"; 1538 regulator-min-microvolt = <850000>; 1539 regulator-max-microvolt = <1120000>; 1540 regulator-ramp-delay = <6250>; 1541 regulator-enable-ramp-delay = <240>; 1542 regulator-always-on; 1543 }; 1544 1545 vusb { 1546 regulator-name = "pp3070_vusb"; 1547 regulator-min-microvolt = <3000000>; 1548 regulator-max-microvolt = <3070000>; 1549 regulator-enable-ramp-delay = <270>; 1550 regulator-always-on; 1551 }; 1552 1553 vxo22 { 1554 regulator-name = "pp2240_vxo22"; 1555 regulator-min-microvolt = <2200000>; 1556 regulator-max-microvolt = <2240000>; 1557 regulator-enable-ramp-delay = <120>; 1558 /* Feeds DCXO internally */ 1559 regulator-always-on; 1560 }; 1561 }; 1562 1563 rtc { 1564 compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; 1565 }; 1566 }; 1567}; 1568 1569&scp { 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&scp_pins>; 1572 firmware-name = "mediatek/mt8186/scp.img"; 1573 memory-region = <&scp_mem>; 1574 status = "okay"; 1575 1576 cros-ec-rpmsg { 1577 compatible = "google,cros-ec-rpmsg"; 1578 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1579 }; 1580}; 1581 1582&spi1 { 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&spi1_pins>; 1585 mediatek,pad-select = <0>; 1586 status = "okay"; 1587 1588 cros_ec: ec@0 { 1589 compatible = "google,cros-ec-spi"; 1590 reg = <0>; 1591 interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; 1592 pinctrl-names = "default"; 1593 pinctrl-0 = <&ec_ap_int>; 1594 spi-max-frequency = <1000000>; 1595 1596 i2c_tunnel: i2c-tunnel { 1597 compatible = "google,cros-ec-i2c-tunnel"; 1598 google,remote-bus = <1>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 }; 1602 1603 typec { 1604 compatible = "google,cros-ec-typec"; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 1608 usb_c0: connector@0 { 1609 compatible = "usb-c-connector"; 1610 reg = <0>; 1611 label = "left"; 1612 power-role = "dual"; 1613 data-role = "host"; 1614 try-power-role = "source"; 1615 }; 1616 1617 usb_c1: connector@1 { 1618 compatible = "usb-c-connector"; 1619 reg = <1>; 1620 label = "right"; 1621 power-role = "dual"; 1622 data-role = "host"; 1623 try-power-role = "source"; 1624 }; 1625 }; 1626 }; 1627}; 1628 1629&spi2 { 1630 pinctrl-names = "default"; 1631 pinctrl-0 = <&spi2_pins>; 1632 cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; 1633 mediatek,pad-select = <0>; 1634 status = "okay"; 1635 1636 tpm@0 { 1637 compatible = "google,cr50"; 1638 reg = <0>; 1639 interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&gsc_int>; 1642 spi-max-frequency = <1000000>; 1643 }; 1644}; 1645 1646&ssusb0 { 1647 status = "okay"; 1648}; 1649 1650&ssusb1 { 1651 status = "okay"; 1652}; 1653 1654&u3phy0 { 1655 status = "okay"; 1656}; 1657 1658&u3phy1 { 1659 status = "okay"; 1660}; 1661 1662&uart0 { 1663 status = "okay"; 1664}; 1665 1666&usb_host0 { 1667 vbus-supply = <&pp3300_s3>; 1668 status = "okay"; 1669}; 1670 1671&usb_host1 { 1672 vbus-supply = <&usb_p1_vbus>; 1673 status = "okay"; 1674}; 1675 1676&watchdog { 1677 mediatek,reset-by-toprgu; 1678}; 1679 1680#include <arm/cros-ec-keyboard.dtsi> 1681#include <arm/cros-ec-sbs.dtsi> 1682