1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "mt8173.dtsi"
11
12/ {
13	aliases {
14		mmc0 = &mmc0;
15		mmc1 = &mmc1;
16		mmc2 = &mmc3;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	backlight: backlight {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 1000000>;
27		power-supply = <&bl_fixed_reg>;
28		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
29
30		pinctrl-names = "default";
31		pinctrl-0 = <&panel_backlight_en_pins>;
32		status = "okay";
33	};
34
35	bl_fixed_reg: fixedregulator2 {
36		compatible = "regulator-fixed";
37		regulator-name = "bl_fixed";
38		regulator-min-microvolt = <1800000>;
39		regulator-max-microvolt = <1800000>;
40		startup-delay-us = <1000>;
41		enable-active-high;
42		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
43		pinctrl-names = "default";
44		pinctrl-0 = <&bl_fixed_pins>;
45	};
46
47	chosen {
48		stdout-path = "serial0:115200n8";
49	};
50
51	gpio_keys: gpio-keys {
52		compatible = "gpio-keys";
53		pinctrl-names = "default";
54		pinctrl-0 = <&gpio_keys_pins>;
55
56		switch-lid {
57			label = "Lid";
58			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
59			linux,code = <SW_LID>;
60			linux,input-type = <EV_SW>;
61			wakeup-source;
62		};
63
64		switch-power {
65			label = "Power";
66			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
67			linux,code = <KEY_POWER>;
68			debounce-interval = <30>;
69			wakeup-source;
70		};
71
72		switch-tablet-mode {
73			label = "Tablet_mode";
74			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
75			linux,code = <SW_TABLET_MODE>;
76			linux,input-type = <EV_SW>;
77			wakeup-source;
78		};
79
80		switch-volume-down {
81			label = "Volume_down";
82			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
83			linux,code = <KEY_VOLUMEDOWN>;
84		};
85
86		switch-volume-up {
87			label = "Volume_up";
88			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
89			linux,code = <KEY_VOLUMEUP>;
90		};
91	};
92
93	panel_fixed_3v3: regulator1 {
94		compatible = "regulator-fixed";
95		regulator-name = "PANEL_3V3";
96		regulator-min-microvolt = <3300000>;
97		regulator-max-microvolt = <3300000>;
98		enable-active-high;
99		regulator-boot-on;
100		off-on-delay-us = <500000>;
101		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
102		pinctrl-names = "default";
103		pinctrl-0 = <&panel_fixed_pins>;
104	};
105
106	ps8640_fixed_1v2: regulator2 {
107		compatible = "regulator-fixed";
108		regulator-name = "PS8640_1V2";
109		regulator-min-microvolt = <1200000>;
110		regulator-max-microvolt = <1200000>;
111		regulator-enable-ramp-delay = <2000>;
112		enable-active-high;
113		regulator-boot-on;
114		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
115		pinctrl-names = "default";
116		pinctrl-0 = <&ps8640_fixed_pins>;
117	};
118
119	sdio_fixed_3v3: fixedregulator0 {
120		compatible = "regulator-fixed";
121		regulator-name = "3V3";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
125		pinctrl-names = "default";
126		pinctrl-0 = <&sdio_fixed_3v3_pins>;
127	};
128
129	sound: sound {
130		compatible = "mediatek,mt8173-rt5650";
131		mediatek,audio-codec = <&rt5650 &hdmi0>;
132		mediatek,platform = <&afe>;
133		pinctrl-names = "default";
134		pinctrl-0 = <&aud_i2s2>;
135
136		mediatek,mclk = <1>;
137		codec-capture {
138			sound-dai = <&rt5650 1>;
139		};
140	};
141
142	hdmicon: connector {
143		compatible = "hdmi-connector";
144		label = "hdmi";
145		type = "a";
146		ddc-i2c-bus = <&hdmiddc0>;
147
148		port {
149			hdmi_connector_in: endpoint {
150				remote-endpoint = <&hdmi0_out>;
151			};
152		};
153	};
154
155	watchdog {
156		compatible = "arm,smc-wdt";
157	};
158};
159
160/*
161 * Disable the original MMIO watch dog and switch to the SMC watchdog, which
162 * operates on the same MMIO.
163 */
164&watchdog {
165	status = "disabled";
166};
167
168&mfg_async {
169	domain-supply = <&da9211_vgpu_reg>;
170};
171
172&cec {
173	status = "okay";
174};
175
176&cpu0 {
177	proc-supply = <&mt6397_vpca15_reg>;
178};
179
180&cpu1 {
181	proc-supply = <&mt6397_vpca15_reg>;
182};
183
184&cpu2 {
185	proc-supply = <&da9211_vcpu_reg>;
186	sram-supply = <&mt6397_vsramca7_reg>;
187};
188
189&cpu3 {
190	proc-supply = <&da9211_vcpu_reg>;
191	sram-supply = <&mt6397_vsramca7_reg>;
192};
193
194&cpu_thermal {
195	sustainable-power = <4500>; /* milliwatts */
196	trips {
197		threshold: trip-point0 {
198			temperature = <60000>;
199		};
200
201		target: trip-point1 {
202			temperature = <65000>;
203		};
204	};
205};
206
207&dsi0 {
208	status = "okay";
209	ports {
210		port {
211			dsi0_out: endpoint {
212				remote-endpoint = <&ps8640_in>;
213			};
214		};
215	};
216};
217
218&dpi0 {
219	status = "okay";
220};
221
222&hdmi0 {
223	status = "okay";
224	ports {
225		port@1 {
226			reg = <1>;
227
228			hdmi0_out: endpoint {
229				remote-endpoint = <&hdmi_connector_in>;
230			};
231		};
232	};
233};
234
235&hdmi_phy {
236	status = "okay";
237	mediatek,ibias = <0xc>;
238};
239
240&i2c0 {
241	status = "okay";
242
243	rt5650: audio-codec@1a {
244		compatible = "realtek,rt5650";
245		reg = <0x1a>;
246		avdd-supply = <&mt6397_vgp1_reg>;
247		cpvdd-supply = <&mt6397_vcama_reg>;
248		interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_BOTH>;
249		pinctrl-names = "default";
250		pinctrl-0 = <&rt5650_irq>;
251		#sound-dai-cells = <1>;
252		realtek,dmic1-data-pin = <2>;
253		realtek,jd-mode = <2>;
254	};
255
256	ps8640: edp-bridge@8 {
257		compatible = "parade,ps8640";
258		reg = <0x8>;
259		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
260		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
261		pinctrl-names = "default";
262		pinctrl-0 = <&ps8640_pins>;
263		vdd12-supply = <&ps8640_fixed_1v2>;
264		vdd33-supply = <&mt6397_vgp2_reg>;
265
266		ports {
267			#address-cells = <1>;
268			#size-cells = <0>;
269
270			port@0 {
271				reg = <0>;
272
273				ps8640_in: endpoint {
274					remote-endpoint = <&dsi0_out>;
275				};
276			};
277
278			port@1 {
279				reg = <1>;
280
281				ps8640_out: endpoint {
282					remote-endpoint = <&panel_in>;
283				};
284			};
285		};
286
287		aux-bus {
288			panel: panel {
289				compatible = "edp-panel";
290				power-supply = <&panel_fixed_3v3>;
291				backlight = <&backlight>;
292
293				port {
294					panel_in: endpoint {
295						remote-endpoint = <&ps8640_out>;
296					};
297				};
298			};
299		};
300	};
301};
302
303&i2c1 {
304	clock-frequency = <1500000>;
305	status = "okay";
306
307	da9211: da9211@68 {
308		compatible = "dlg,da9211";
309		reg = <0x68>;
310		interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
311
312		regulators {
313			da9211_vcpu_reg: BUCKA {
314				regulator-name = "VBUCKA";
315				regulator-min-microvolt = < 700000>;
316				regulator-max-microvolt = <1310000>;
317				regulator-min-microamp = <2000000>;
318				regulator-max-microamp = <4400000>;
319				regulator-ramp-delay = <10000>;
320				regulator-always-on;
321				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
322							   DA9211_BUCK_MODE_AUTO>;
323			};
324
325			da9211_vgpu_reg: BUCKB {
326				regulator-name = "VBUCKB";
327				regulator-min-microvolt = < 700000>;
328				regulator-max-microvolt = <1310000>;
329				regulator-min-microamp = <2000000>;
330				regulator-max-microamp = <3000000>;
331				regulator-ramp-delay = <10000>;
332			};
333		};
334	};
335};
336
337&i2c2 {
338	status = "okay";
339
340	tpm: tpm@20 {
341		compatible = "infineon,slb9645tt";
342		reg = <0x20>;
343		powered-while-suspended;
344	};
345};
346
347&i2c3 {
348	clock-frequency = <400000>;
349	status = "okay";
350
351	touchscreen: touchscreen@10 {
352		compatible = "elan,ekth3500";
353		reg = <0x10>;
354		interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
355	};
356};
357
358&i2c4 {
359	clock-frequency = <400000>;
360	status = "okay";
361	pinctrl-names = "default";
362	pinctrl-0 = <&trackpad_irq>;
363
364	trackpad: trackpad@15 {
365		compatible = "elan,ekth3000";
366		interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
367		reg = <0x15>;
368		vcc-supply = <&mt6397_vgp6_reg>;
369		wakeup-source;
370	};
371};
372
373&mipi_tx0 {
374	status = "okay";
375};
376
377&mmc0 {
378	status = "okay";
379	pinctrl-names = "default", "state_uhs";
380	pinctrl-0 = <&mmc0_pins_default>;
381	pinctrl-1 = <&mmc0_pins_uhs>;
382	bus-width = <8>;
383	max-frequency = <200000000>;
384	cap-mmc-highspeed;
385	mmc-hs200-1_8v;
386	mmc-hs400-1_8v;
387	cap-mmc-hw-reset;
388	hs400-ds-delay = <0x14015>;
389	mediatek,hs200-cmd-int-delay = <30>;
390	mediatek,hs400-cmd-int-delay = <14>;
391	mediatek,hs400-cmd-resp-sel-rising;
392	vmmc-supply = <&mt6397_vemc_3v3_reg>;
393	vqmmc-supply = <&mt6397_vio18_reg>;
394	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
395	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
396	non-removable;
397};
398
399&mmc1 {
400	status = "okay";
401	pinctrl-names = "default", "state_uhs";
402	pinctrl-0 = <&mmc1_pins_default>;
403	pinctrl-1 = <&mmc1_pins_uhs>;
404	bus-width = <4>;
405	max-frequency = <200000000>;
406	cap-sd-highspeed;
407	sd-uhs-sdr50;
408	sd-uhs-sdr104;
409	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
410	vmmc-supply = <&mt6397_vmch_reg>;
411	vqmmc-supply = <&mt6397_vmc_reg>;
412};
413
414&mmc3 {
415	status = "okay";
416	pinctrl-names = "default", "state_uhs";
417	pinctrl-0 = <&mmc3_pins_default>;
418	pinctrl-1 = <&mmc3_pins_uhs>;
419	bus-width = <4>;
420	max-frequency = <200000000>;
421	cap-sd-highspeed;
422	sd-uhs-sdr50;
423	sd-uhs-sdr104;
424	keep-power-in-suspend;
425	wakeup-source;
426	cap-sdio-irq;
427	vmmc-supply = <&sdio_fixed_3v3>;
428	vqmmc-supply = <&mt6397_vgp3_reg>;
429	non-removable;
430	cap-power-off-card;
431
432	#address-cells = <1>;
433	#size-cells = <0>;
434
435	btmrvl: btmrvl@2 {
436		compatible = "marvell,sd8897-bt";
437		reg = <2>;
438		interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>;
439		marvell,wakeup-pin = /bits/ 16 <0x0d>;
440		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
441	};
442
443	mwifiex: mwifiex@1 {
444		compatible = "marvell,sd8897";
445		reg = <1>;
446		interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>;
447		marvell,wakeup-pin = <3>;
448	};
449};
450
451&nor_flash {
452	status = "okay";
453	pinctrl-names = "default";
454	pinctrl-0 = <&nor_gpio1_pins>;
455
456	flash@0 {
457		compatible = "jedec,spi-nor";
458		reg = <0>;
459		spi-max-frequency = <50000000>;
460	};
461};
462
463&pio {
464	gpio-line-names = "EC_INT_1V8",
465			  "SD_CD_L",
466			  "ALC5514_IRQ",
467			  "ALC5650_IRQ",
468			  /*
469			   * AP_FLASH_WP_L is crossystem ABI. Schematics
470			   * call it SFWP_B.
471			   */
472			  "AP_FLASH_WP_L",
473			  "SFIN",
474			  "SFCS0",
475			  "SFHOLD",
476			  "SFOUT",
477			  "SFCK",
478			  "WRAP_EVENT_S_EINT10",
479			  "PMU_INT",
480			  "I2S2_WS_ALC5650",
481			  "I2S2_BCK_ALC5650",
482			  "PWR_BTN_1V8",
483			  "DA9212_IRQ",
484			  "IDDIG",
485			  "WATCHDOG",
486			  "CEC",
487			  "HDMISCK",
488			  "HDMISD",
489			  "HTPLG",
490			  "MSDC3_DAT0",
491			  "MSDC3_DAT1",
492			  "MSDC3_DAT2",
493			  "MSDC3_DAT3",
494			  "MSDC3_CLK",
495			  "MSDC3_CMD",
496			  "USB_C0_OC_FLAGB",
497			  "USBA_OC1_L",
498			  "PS8640_1V2_ENABLE",
499			  "THERM_ALERT_N",
500			  "PANEL_LCD_POWER_EN",
501			  "ANX7688_CHIP_PD_C",
502			  "EC_IN_RW_1V8",
503			  "ANX7688_1V_EN_C",
504			  "USB_DP_HPD_C",
505			  "TPM_DAVINT_N",
506			  "MARVELL8897_IRQ",
507			  "EN_USB_A0_PWR",
508			  "USBA_A0_OC_L",
509			  "EN_PP3300_DX_EDP",
510			  "",
511			  "SOC_I2C2_1V8_SDA_400K",
512			  "SOC_I2C2_1V8_SCL_400K",
513			  "SOC_I2C0_1V8_SDA_400K",
514			  "SOC_I2C0_1V8_SCL_400K",
515			  "EMMC_ID1",
516			  "EMMC_ID0",
517			  "MEM_CONFIG3",
518			  "EMMC_ID2",
519			  "MEM_CONFIG1",
520			  "MEM_CONFIG2",
521			  "BRD_ID2",
522			  "MEM_CONFIG0",
523			  "BRD_ID0",
524			  "BRD_ID1",
525			  "EMMC_DAT0",
526			  "EMMC_DAT1",
527			  "EMMC_DAT2",
528			  "EMMC_DAT3",
529			  "EMMC_DAT4",
530			  "EMMC_DAT5",
531			  "EMMC_DAT6",
532			  "EMMC_DAT7",
533			  "EMMC_CLK",
534			  "EMMC_CMD",
535			  "EMMC_RCLK",
536			  "PLT_RST_L",
537			  "LID_OPEN_1V8_L",
538			  "AUDIO_SPI_MISO_R",
539			  "",
540			  "AC_OK_1V8",
541			  "SD_DATA0",
542			  "SD_DATA1",
543			  "SD_DATA2",
544			  "SD_DATA3",
545			  "SD_CLK",
546			  "SD_CMD",
547			  "PWRAP_SPI0_MI",
548			  "PWRAP_SPI0_MO",
549			  "PWRAP_SPI0_CK",
550			  "PWRAP_SPI0_CSN",
551			  "",
552			  "",
553			  "WIFI_PDN",
554			  "RTC32K_1V8",
555			  "DISP_PWM0",
556			  "TOUCHSCREEN_INT_L",
557			  "",
558			  "SRCLKENA0",
559			  "SRCLKENA1",
560			  "PS8640_MODE_CONF",
561			  "TOUCHSCREEN_RESET_R",
562			  "PLATFORM_PROCHOT_L",
563			  "PANEL_POWER_EN",
564			  "REC_MODE_L",
565			  "EC_FW_UPDATE_L",
566			  "ACCEL2_INT_L",
567			  "HDMI_DP_INT",
568			  "ACCELGYRO3_INT_L",
569			  "ACCELGYRO4_INT_L",
570			  "SPI_EC_CLK",
571			  "SPI_EC_MI",
572			  "SPI_EC_MO",
573			  "SPI_EC_CSN",
574			  "SOC_I2C3_1V8_SDA_400K",
575			  "SOC_I2C3_1V8_SCL_400K",
576			  "",
577			  "",
578			  "",
579			  "",
580			  "",
581			  "",
582			  "",
583			  "PS8640_SYSRSTN_1V8",
584			  "APIN_MAX98090_DOUT2",
585			  "TP_INT_1V8_L_R",
586			  "RST_USB_HUB_R",
587			  "BT_WAKE_L",
588			  "ACCEL1_INT_L",
589			  "TABLET_MODE_L",
590			  "",
591			  "V_UP_IN_L_R",
592			  "V_DOWN_IN_L_R",
593			  "SOC_I2C1_1V8_SDA_1M",
594			  "SOC_I2C1_1V8_SCL_1M",
595			  "PS8640_PDN_1V8",
596			  "MAX98090_LRCLK",
597			  "MAX98090_BCLK",
598			  "MAX98090_MCLK",
599			  "APOUT_MAX98090_DIN",
600			  "APIN_MAX98090_DOUT",
601			  "SOC_I2C4_1V8_SDA_400K",
602			  "SOC_I2C4_1V8_SCL_400K";
603
604	aud_i2s2: aud_i2s2 {
605		pins1 {
606			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
607				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
608				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
609				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
610				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
611				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
612				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
613			bias-pull-down;
614		};
615	};
616
617	bl_fixed_pins: bl_fixed_pins {
618		pins1 {
619			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
620			output-low;
621		};
622	};
623
624	bt_wake_pins: bt_wake_pins {
625		pins1 {
626			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
627			bias-pull-up;
628		};
629	};
630
631	disp_pwm0_pins: disp_pwm0_pins {
632		pins1 {
633			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
634			output-low;
635		};
636	};
637
638	gpio_keys_pins: gpio_keys_pins {
639		volume_pins {
640			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
641				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
642			bias-pull-up;
643		};
644
645		tablet_mode_pins {
646			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
647			bias-pull-up;
648		};
649	};
650
651	hdmi_mux_pins: hdmi_mux_pins {
652		pins1 {
653			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
654		};
655	};
656
657	i2c1_pins_a: i2c1 {
658		da9211_pins {
659			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
660			bias-pull-up;
661		};
662	};
663
664	mmc0_pins_default: mmc0default {
665		pins_cmd_dat {
666			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
667				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
668				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
669				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
670				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
671				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
672				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
673				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
674				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
675			bias-pull-up;
676		};
677
678		pins_clk {
679			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
680			bias-pull-down;
681		};
682
683		pins_rst {
684			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
685			bias-pull-up;
686		};
687	};
688
689	mmc1_pins_default: mmc1default {
690		pins_cmd_dat {
691			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
692				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
693				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
694				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
695				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
696			input-enable;
697			drive-strength = <MTK_DRIVE_4mA>;
698			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
699		};
700
701		pins_clk {
702			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
703			bias-pull-down;
704			drive-strength = <MTK_DRIVE_4mA>;
705		};
706
707		pins_insert {
708			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
709			bias-pull-up;
710		};
711	};
712
713	mmc3_pins_default: mmc3default {
714		pins_dat {
715			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
716				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
717				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
718				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
719			input-enable;
720			drive-strength = <MTK_DRIVE_8mA>;
721			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
722		};
723
724		pins_cmd {
725			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
726			input-enable;
727			drive-strength = <MTK_DRIVE_8mA>;
728			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
729		};
730
731		pins_clk {
732			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
733			bias-pull-down;
734			drive-strength = <MTK_DRIVE_8mA>;
735		};
736	};
737
738	mmc0_pins_uhs: mmc0 {
739		pins_cmd_dat {
740			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
741				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
742				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
743				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
744				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
745				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
746				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
747				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
748				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
749			input-enable;
750			drive-strength = <MTK_DRIVE_6mA>;
751			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
752		};
753
754		pins_clk {
755			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
756			drive-strength = <MTK_DRIVE_6mA>;
757			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
758		};
759
760		pins_ds {
761			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
762			drive-strength = <MTK_DRIVE_10mA>;
763			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
764		};
765
766		pins_rst {
767			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
768			bias-pull-up;
769		};
770	};
771
772	mmc1_pins_uhs: mmc1 {
773		pins_cmd_dat {
774			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
775				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
776				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
777				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
778				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
779			input-enable;
780			drive-strength = <MTK_DRIVE_6mA>;
781			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
782		};
783
784		pins_clk {
785			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
786			drive-strength = <MTK_DRIVE_8mA>;
787			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
788		};
789	};
790
791	mmc3_pins_uhs: mmc3 {
792		pins_dat {
793			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
794				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
795				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
796				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
797			input-enable;
798			drive-strength = <MTK_DRIVE_8mA>;
799			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
800		};
801
802		pins_cmd {
803			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
804			input-enable;
805			drive-strength = <MTK_DRIVE_8mA>;
806			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
807		};
808
809		pins_clk {
810			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
811			drive-strength = <MTK_DRIVE_8mA>;
812			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
813		};
814	};
815
816	nor_gpio1_pins: nor {
817		pins1 {
818			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
819				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
820				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
821			input-enable;
822			drive-strength = <MTK_DRIVE_4mA>;
823			bias-pull-up;
824		};
825
826		pins2 {
827			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
828			drive-strength = <MTK_DRIVE_4mA>;
829			bias-pull-up;
830		};
831
832		pins_clk {
833			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
834			input-enable;
835			drive-strength = <MTK_DRIVE_4mA>;
836			bias-pull-up;
837		};
838	};
839
840	panel_backlight_en_pins: panel_backlight_en_pins {
841		pins1 {
842			pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
843		};
844	};
845
846	panel_fixed_pins: panel_fixed_pins {
847		pins1 {
848			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
849		};
850	};
851
852	ps8640_pins: ps8640_pins {
853		pins1 {
854			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
855				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
856				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
857		};
858	};
859
860	ps8640_fixed_pins: ps8640_fixed_pins {
861		pins1 {
862			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
863		};
864	};
865
866	rt5650_irq: rt5650_irq {
867		pins1 {
868			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
869			bias-pull-down;
870		};
871	};
872
873	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
874		pins1 {
875			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
876			output-low;
877		};
878	};
879
880	spi_pins_a: spi1 {
881		pins1 {
882			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
883			bias-pull-up;
884		};
885
886		pins_spi {
887			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
888				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
889				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
890				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
891			bias-disable;
892		};
893	};
894
895	trackpad_irq: trackpad_irq {
896		pins1 {
897			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
898			input-enable;
899			bias-pull-up;
900		};
901	};
902
903	usb_pins: usb {
904		pins1 {
905			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
906			output-high;
907			bias-disable;
908		};
909	};
910
911	wifi_wake_pins: wifi_wake_pins {
912		pins1 {
913			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
914			bias-pull-up;
915		};
916	};
917};
918
919&pwm0 {
920	pinctrl-names = "default";
921	pinctrl-0 = <&disp_pwm0_pins>;
922	status = "okay";
923};
924
925&pwrap {
926	pmic: pmic {
927		compatible = "mediatek,mt6397";
928		#address-cells = <1>;
929		#size-cells = <1>;
930		interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
931		interrupt-controller;
932		#interrupt-cells = <2>;
933
934		clock: mt6397clock {
935			compatible = "mediatek,mt6397-clk";
936			#clock-cells = <1>;
937		};
938
939		pio6397: pinctrl {
940			compatible = "mediatek,mt6397-pinctrl";
941			gpio-controller;
942			#gpio-cells = <2>;
943		};
944
945		regulator: mt6397regulator {
946			compatible = "mediatek,mt6397-regulator";
947
948			mt6397_vpca15_reg: buck_vpca15 {
949				regulator-compatible = "buck_vpca15";
950				regulator-name = "vpca15";
951				regulator-min-microvolt = < 700000>;
952				regulator-max-microvolt = <1350000>;
953				regulator-ramp-delay = <12500>;
954				regulator-always-on;
955				regulator-allowed-modes = <0 1>;
956			};
957
958			mt6397_vpca7_reg: buck_vpca7 {
959				regulator-compatible = "buck_vpca7";
960				regulator-name = "vpca7";
961				regulator-min-microvolt = < 700000>;
962				regulator-max-microvolt = <1350000>;
963				regulator-ramp-delay = <12500>;
964				regulator-enable-ramp-delay = <115>;
965				regulator-always-on;
966			};
967
968			mt6397_vsramca15_reg: buck_vsramca15 {
969				regulator-compatible = "buck_vsramca15";
970				regulator-name = "vsramca15";
971				regulator-min-microvolt = < 700000>;
972				regulator-max-microvolt = <1350000>;
973				regulator-ramp-delay = <12500>;
974				regulator-always-on;
975			};
976
977			mt6397_vsramca7_reg: buck_vsramca7 {
978				regulator-compatible = "buck_vsramca7";
979				regulator-name = "vsramca7";
980				regulator-min-microvolt = < 700000>;
981				regulator-max-microvolt = <1350000>;
982				regulator-ramp-delay = <12500>;
983				regulator-always-on;
984			};
985
986			mt6397_vcore_reg: buck_vcore {
987				regulator-compatible = "buck_vcore";
988				regulator-name = "vcore";
989				regulator-min-microvolt = < 700000>;
990				regulator-max-microvolt = <1350000>;
991				regulator-ramp-delay = <12500>;
992				regulator-always-on;
993			};
994
995			mt6397_vgpu_reg: buck_vgpu {
996				regulator-compatible = "buck_vgpu";
997				regulator-name = "vgpu";
998				regulator-min-microvolt = < 700000>;
999				regulator-max-microvolt = <1350000>;
1000				regulator-ramp-delay = <12500>;
1001				regulator-enable-ramp-delay = <115>;
1002			};
1003
1004			mt6397_vdrm_reg: buck_vdrm {
1005				regulator-compatible = "buck_vdrm";
1006				regulator-name = "vdrm";
1007				regulator-min-microvolt = <1200000>;
1008				regulator-max-microvolt = <1400000>;
1009				regulator-ramp-delay = <12500>;
1010				regulator-always-on;
1011			};
1012
1013			mt6397_vio18_reg: buck_vio18 {
1014				regulator-compatible = "buck_vio18";
1015				regulator-name = "vio18";
1016				regulator-min-microvolt = <1620000>;
1017				regulator-max-microvolt = <1980000>;
1018				regulator-ramp-delay = <12500>;
1019				regulator-always-on;
1020			};
1021
1022			mt6397_vtcxo_reg: ldo_vtcxo {
1023				regulator-compatible = "ldo_vtcxo";
1024				regulator-name = "vtcxo";
1025				regulator-always-on;
1026			};
1027
1028			mt6397_va28_reg: ldo_va28 {
1029				regulator-compatible = "ldo_va28";
1030				regulator-name = "va28";
1031			};
1032
1033			mt6397_vcama_reg: ldo_vcama {
1034				regulator-compatible = "ldo_vcama";
1035				regulator-name = "vcama";
1036				regulator-min-microvolt = <1800000>;
1037				regulator-max-microvolt = <1800000>;
1038				regulator-enable-ramp-delay = <218>;
1039			};
1040
1041			mt6397_vio28_reg: ldo_vio28 {
1042				regulator-compatible = "ldo_vio28";
1043				regulator-name = "vio28";
1044				regulator-always-on;
1045			};
1046
1047			mt6397_vusb_reg: ldo_vusb {
1048				regulator-compatible = "ldo_vusb";
1049				regulator-name = "vusb";
1050			};
1051
1052			mt6397_vmc_reg: ldo_vmc {
1053				regulator-compatible = "ldo_vmc";
1054				regulator-name = "vmc";
1055				regulator-min-microvolt = <1800000>;
1056				regulator-max-microvolt = <3300000>;
1057				regulator-enable-ramp-delay = <218>;
1058			};
1059
1060			mt6397_vmch_reg: ldo_vmch {
1061				regulator-compatible = "ldo_vmch";
1062				regulator-name = "vmch";
1063				regulator-min-microvolt = <3000000>;
1064				regulator-max-microvolt = <3300000>;
1065				regulator-enable-ramp-delay = <218>;
1066			};
1067
1068			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1069				regulator-compatible = "ldo_vemc3v3";
1070				regulator-name = "vemc_3v3";
1071				regulator-min-microvolt = <3000000>;
1072				regulator-max-microvolt = <3300000>;
1073				regulator-enable-ramp-delay = <218>;
1074			};
1075
1076			mt6397_vgp1_reg: ldo_vgp1 {
1077				regulator-compatible = "ldo_vgp1";
1078				regulator-name = "vcamd";
1079				regulator-min-microvolt = <1800000>;
1080				regulator-max-microvolt = <1800000>;
1081				regulator-enable-ramp-delay = <240>;
1082			};
1083
1084			mt6397_vgp2_reg: ldo_vgp2 {
1085				regulator-compatible = "ldo_vgp2";
1086				regulator-name = "vcamio";
1087				regulator-min-microvolt = <3300000>;
1088				regulator-max-microvolt = <3300000>;
1089				regulator-enable-ramp-delay = <218>;
1090			};
1091
1092			mt6397_vgp3_reg: ldo_vgp3 {
1093				regulator-compatible = "ldo_vgp3";
1094				regulator-name = "vcamaf";
1095				regulator-min-microvolt = <1800000>;
1096				regulator-max-microvolt = <1800000>;
1097				regulator-enable-ramp-delay = <218>;
1098			};
1099
1100			mt6397_vgp4_reg: ldo_vgp4 {
1101				regulator-compatible = "ldo_vgp4";
1102				regulator-name = "vgp4";
1103				regulator-min-microvolt = <1200000>;
1104				regulator-max-microvolt = <3300000>;
1105				regulator-enable-ramp-delay = <218>;
1106			};
1107
1108			mt6397_vgp5_reg: ldo_vgp5 {
1109				regulator-compatible = "ldo_vgp5";
1110				regulator-name = "vgp5";
1111				regulator-min-microvolt = <1200000>;
1112				regulator-max-microvolt = <3000000>;
1113				regulator-enable-ramp-delay = <218>;
1114			};
1115
1116			mt6397_vgp6_reg: ldo_vgp6 {
1117				regulator-compatible = "ldo_vgp6";
1118				regulator-name = "vgp6";
1119				regulator-min-microvolt = <3300000>;
1120				regulator-max-microvolt = <3300000>;
1121				regulator-enable-ramp-delay = <218>;
1122				regulator-always-on;
1123			};
1124
1125			mt6397_vibr_reg: ldo_vibr {
1126				regulator-compatible = "ldo_vibr";
1127				regulator-name = "vibr";
1128				regulator-min-microvolt = <1300000>;
1129				regulator-max-microvolt = <3300000>;
1130				regulator-enable-ramp-delay = <218>;
1131			};
1132		};
1133
1134		rtc: mt6397rtc {
1135			compatible = "mediatek,mt6397-rtc";
1136		};
1137
1138		syscfg_pctl_pmic: syscon@c000 {
1139			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1140				     "syscon";
1141			reg = <0 0x0000c000 0 0x0108>;
1142		};
1143	};
1144};
1145
1146&spi {
1147	pinctrl-names = "default";
1148	pinctrl-0 = <&spi_pins_a>;
1149	mediatek,pad-select = <1>;
1150	status = "okay";
1151	/* clients */
1152	cros_ec: ec@0 {
1153		compatible = "google,cros-ec-spi";
1154		reg = <0x0>;
1155		spi-max-frequency = <12000000>;
1156		interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>;
1157		google,cros-ec-spi-msg-delay = <500>;
1158		wakeup-source;
1159
1160		i2c_tunnel: i2c-tunnel0 {
1161			compatible = "google,cros-ec-i2c-tunnel";
1162			google,remote-bus = <0>;
1163			#address-cells = <1>;
1164			#size-cells = <0>;
1165
1166			battery: sbs-battery@b {
1167				compatible = "sbs,sbs-battery";
1168				reg = <0xb>;
1169				sbs,i2c-retry-count = <2>;
1170				sbs,poll-retry-count = <1>;
1171			};
1172		};
1173	};
1174};
1175
1176&ssusb {
1177	dr_mode = "host";
1178	wakeup-source;
1179	vusb33-supply = <&mt6397_vusb_reg>;
1180	status = "okay";
1181};
1182
1183&thermal {
1184	bank0-supply = <&mt6397_vpca15_reg>;
1185	bank1-supply = <&da9211_vcpu_reg>;
1186};
1187
1188&uart0 {
1189	status = "okay";
1190};
1191
1192&usb_host {
1193	pinctrl-names = "default";
1194	pinctrl-0 = <&usb_pins>;
1195	vusb33-supply = <&mt6397_vusb_reg>;
1196	status = "okay";
1197};
1198
1199#include <arm/cros-ec-keyboard.dtsi>
1200