1127474Stjr// SPDX-License-Identifier: GPL-2.0
2127474Stjr/*
3127474Stjr * Copyright (c) 2020 MediaTek Inc.
4127474Stjr * Copyright (c) 2020 BayLibre, SAS.
5127474Stjr * Author: Fabien Parent <fparent@baylibre.com>
6127474Stjr */
7127474Stjr
8127474Stjr#include <dt-bindings/clock/mt8167-clk.h>
9174990Sache#include <dt-bindings/memory/mt8167-larb-port.h>
10127474Stjr#include <dt-bindings/power/mt8167-power.h>
11127474Stjr
12127474Stjr#include "mt8167-pinfunc.h"
13127474Stjr
14127474Stjr#include "mt8516.dtsi"
15127474Stjr
16127474Stjr/ {
17127474Stjr	compatible = "mediatek,mt8167";
18127474Stjr
19127474Stjr	soc {
20127474Stjr		topckgen: topckgen@10000000 {
21127474Stjr			compatible = "mediatek,mt8167-topckgen", "syscon";
22127474Stjr			reg = <0 0x10000000 0 0x1000>;
23127474Stjr			#clock-cells = <1>;
24174990Sache		};
25127474Stjr
26127474Stjr		infracfg: infracfg@10001000 {
27127474Stjr			compatible = "mediatek,mt8167-infracfg", "syscon";
28127474Stjr			reg = <0 0x10001000 0 0x1000>;
29127474Stjr			#clock-cells = <1>;
30127474Stjr		};
31127474Stjr
32127474Stjr		apmixedsys: apmixedsys@10018000 {
33127474Stjr			compatible = "mediatek,mt8167-apmixedsys", "syscon";
34127474Stjr			reg = <0 0x10018000 0 0x710>;
35127474Stjr			#clock-cells = <1>;
36127474Stjr		};
37127474Stjr
38127474Stjr		scpsys: syscon@10006000 {
39174990Sache			compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
40127474Stjr			reg = <0 0x10006000 0 0x1000>;
41127474Stjr
42127474Stjr			spm: power-controller {
43127474Stjr				compatible = "mediatek,mt8167-power-controller";
44127474Stjr				#address-cells = <1>;
45127474Stjr				#size-cells = <0>;
46127474Stjr				#power-domain-cells = <1>;
47127474Stjr
48127474Stjr				/* power domains of the SoC */
49174990Sache				power-domain@MT8167_POWER_DOMAIN_MM {
50127474Stjr					reg = <MT8167_POWER_DOMAIN_MM>;
51127474Stjr					clocks = <&topckgen CLK_TOP_SMI_MM>;
52127474Stjr					clock-names = "mm";
53127474Stjr					#power-domain-cells = <0>;
54127474Stjr					mediatek,infracfg = <&infracfg>;
55127474Stjr				};
56127474Stjr
57127474Stjr				power-domain@MT8167_POWER_DOMAIN_VDEC {
58127474Stjr					reg = <MT8167_POWER_DOMAIN_VDEC>;
59127474Stjr					clocks = <&topckgen CLK_TOP_SMI_MM>,
60127474Stjr						 <&topckgen CLK_TOP_RG_VDEC>;
61127474Stjr					clock-names = "mm", "vdec";
62127474Stjr					#power-domain-cells = <0>;
63127474Stjr				};
64127474Stjr
65127474Stjr				power-domain@MT8167_POWER_DOMAIN_ISP {
66127474Stjr					reg = <MT8167_POWER_DOMAIN_ISP>;
67127474Stjr					clocks = <&topckgen CLK_TOP_SMI_MM>;
68127474Stjr					clock-names = "mm";
69127474Stjr					#power-domain-cells = <0>;
70127474Stjr				};
71127474Stjr
72127474Stjr				power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
73127474Stjr					reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
74127474Stjr					clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75127474Stjr						 <&topckgen CLK_TOP_RG_SLOW_MFG>;
76127474Stjr					clock-names = "axi_mfg", "mfg";
77127474Stjr					#address-cells = <1>;
78127474Stjr					#size-cells = <0>;
79127474Stjr					#power-domain-cells = <1>;
80127474Stjr					mediatek,infracfg = <&infracfg>;
81127474Stjr
82127474Stjr					power-domain@MT8167_POWER_DOMAIN_MFG_2D {
83174990Sache						reg = <MT8167_POWER_DOMAIN_MFG_2D>;
84127474Stjr						#address-cells = <1>;
85127474Stjr						#size-cells = <0>;
86127474Stjr						#power-domain-cells = <1>;
87127474Stjr
88127474Stjr						power-domain@MT8167_POWER_DOMAIN_MFG {
89127474Stjr							reg = <MT8167_POWER_DOMAIN_MFG>;
90127474Stjr							#power-domain-cells = <0>;
91127474Stjr							mediatek,infracfg = <&infracfg>;
92127474Stjr						};
93127474Stjr					};
94127474Stjr				};
95127474Stjr
96127474Stjr				power-domain@MT8167_POWER_DOMAIN_CONN {
97127474Stjr					reg = <MT8167_POWER_DOMAIN_CONN>;
98127474Stjr					#power-domain-cells = <0>;
99127474Stjr					mediatek,infracfg = <&infracfg>;
100127474Stjr				};
101127474Stjr			};
102127474Stjr		};
103127474Stjr
104127474Stjr		imgsys: syscon@15000000 {
105127474Stjr			compatible = "mediatek,mt8167-imgsys", "syscon";
106			reg = <0 0x15000000 0 0x1000>;
107			#clock-cells = <1>;
108		};
109
110		vdecsys: syscon@16000000 {
111			compatible = "mediatek,mt8167-vdecsys", "syscon";
112			reg = <0 0x16000000 0 0x1000>;
113			#clock-cells = <1>;
114		};
115
116		pio: pinctrl@1000b000 {
117			compatible = "mediatek,mt8167-pinctrl";
118			reg = <0 0x1000b000 0 0x1000>;
119			mediatek,pctl-regmap = <&syscfg_pctl>;
120			gpio-controller;
121			#gpio-cells = <2>;
122			interrupt-controller;
123			#interrupt-cells = <2>;
124			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
125		};
126
127		mmsys: syscon@14000000 {
128			compatible = "mediatek,mt8167-mmsys", "syscon";
129			reg = <0 0x14000000 0 0x1000>;
130			#clock-cells = <1>;
131		};
132
133		smi_common: smi@14017000 {
134			compatible = "mediatek,mt8167-smi-common";
135			reg = <0 0x14017000 0 0x1000>;
136			clocks = <&mmsys CLK_MM_SMI_COMMON>,
137				 <&mmsys CLK_MM_SMI_COMMON>;
138			clock-names = "apb", "smi";
139			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
140		};
141
142		larb0: larb@14016000 {
143			compatible = "mediatek,mt8167-smi-larb";
144			reg = <0 0x14016000 0 0x1000>;
145			mediatek,smi = <&smi_common>;
146			clocks = <&mmsys CLK_MM_SMI_LARB0>,
147				 <&mmsys CLK_MM_SMI_LARB0>;
148			clock-names = "apb", "smi";
149			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
150		};
151
152		larb1: larb@15001000 {
153			compatible = "mediatek,mt8167-smi-larb";
154			reg = <0 0x15001000 0 0x1000>;
155			mediatek,smi = <&smi_common>;
156			clocks = <&imgsys CLK_IMG_LARB1_SMI>,
157				 <&imgsys CLK_IMG_LARB1_SMI>;
158			clock-names = "apb", "smi";
159			power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
160		};
161
162		larb2: larb@16010000 {
163			compatible = "mediatek,mt8167-smi-larb";
164			reg = <0 0x16010000 0 0x1000>;
165			mediatek,smi = <&smi_common>;
166			clocks = <&vdecsys CLK_VDEC_CKEN>,
167				 <&vdecsys CLK_VDEC_LARB1_CKEN>;
168			clock-names = "apb", "smi";
169			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
170		};
171
172		iommu: m4u@10203000 {
173			compatible = "mediatek,mt8167-m4u";
174			reg = <0 0x10203000 0 0x1000>;
175			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
176			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
177			#iommu-cells = <1>;
178		};
179	};
180};
181