1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	compatible = "mediatek,mt6755";
12	interrupt-parent = <&sysirq>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	psci {
17		compatible = "arm,psci-0.2";
18		method = "smc";
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-a53";
28			enable-method = "psci";
29			reg = <0x000>;
30		};
31
32		cpu1: cpu@1 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			enable-method = "psci";
36			reg = <0x001>;
37		};
38
39		cpu2: cpu@2 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			enable-method = "psci";
43			reg = <0x002>;
44		};
45
46		cpu3: cpu@3 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			enable-method = "psci";
50			reg = <0x003>;
51		};
52
53		cpu4: cpu@100 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			enable-method = "psci";
57			reg = <0x100>;
58		};
59
60		cpu5: cpu@101 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			enable-method = "psci";
64			reg = <0x101>;
65		};
66
67		cpu6: cpu@102 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53";
70			enable-method = "psci";
71			reg = <0x102>;
72		};
73
74		cpu7: cpu@103 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			enable-method = "psci";
78			reg = <0x103>;
79		};
80	};
81
82	uart_clk: dummy26m {
83		compatible = "fixed-clock";
84		clock-frequency = <26000000>;
85		#clock-cells = <0>;
86	};
87
88	timer {
89		compatible = "arm,armv8-timer";
90		interrupt-parent = <&gic>;
91		interrupts = <GIC_PPI 13
92			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
93			     <GIC_PPI 14
94			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
95			     <GIC_PPI 11
96			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 10
98			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
99	};
100
101	sysirq: intpol-controller@10200620 {
102		compatible = "mediatek,mt6755-sysirq",
103			     "mediatek,mt6577-sysirq";
104		interrupt-controller;
105		#interrupt-cells = <3>;
106		interrupt-parent = <&gic>;
107		reg = <0 0x10200620 0 0x20>;
108	};
109
110	gic: interrupt-controller@10231000 {
111		compatible = "arm,gic-400";
112		#interrupt-cells = <3>;
113		interrupt-parent = <&gic>;
114		interrupt-controller;
115		reg = <0 0x10231000 0 0x1000>,
116		      <0 0x10232000 0 0x2000>,
117		      <0 0x10234000 0 0x2000>,
118		      <0 0x10236000 0 0x2000>;
119	};
120
121	uart0: serial@11002000 {
122		compatible = "mediatek,mt6755-uart",
123			     "mediatek,mt6577-uart";
124		reg = <0 0x11002000 0 0x400>;
125		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
126		clocks = <&uart_clk>;
127		status = "disabled";
128	};
129
130	uart1: serial@11003000 {
131		compatible = "mediatek,mt6755-uart",
132			     "mediatek,mt6577-uart";
133		reg = <0 0x11003000 0 0x400>;
134		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
135		clocks = <&uart_clk>;
136		status = "disabled";
137	};
138};
139