1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6#include "cn9130.dtsi" /* include SoC device tree */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	chosen {
12		stdout-path = "serial0:115200n8";
13	};
14
15	aliases {
16		i2c0 = &cp0_i2c0;
17		ethernet0 = &cp0_eth0;
18		ethernet1 = &cp0_eth1;
19		ethernet2 = &cp0_eth2;
20		gpio1 = &cp0_gpio1;
21		gpio2 = &cp0_gpio2;
22	};
23
24	memory@0 {
25		device_type = "memory";
26		reg = <0x0 0x0 0x0 0x80000000>;
27	};
28
29	ap0_reg_mmc_vccq: regulator-1 {
30		compatible = "regulator-gpio";
31		regulator-name = "ap0_mmc_vccq";
32		regulator-min-microvolt = <1800000>;
33		regulator-max-microvolt = <3300000>;
34		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
35		states = <1800000 0x1
36			  3300000 0x0>;
37	};
38
39	cp0_reg_usb3_vbus1: regulator-2 {
40		compatible = "regulator-fixed";
41		regulator-name = "cp0-xhci1-vbus";
42		regulator-min-microvolt = <5000000>;
43		regulator-max-microvolt = <5000000>;
44		enable-active-high;
45		gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
46	};
47
48	cp0_usb3_0_phy0: usb-phy-1 {
49		compatible = "usb-nop-xceiv";
50	};
51
52	cp0_usb3_0_phy1: usb-phy-2 {
53		compatible = "usb-nop-xceiv";
54		vcc-supply = <&cp0_reg_usb3_vbus1>;
55	};
56
57	cp0_reg_sd_vccq: regulator-3 {
58		compatible = "regulator-gpio";
59		regulator-name = "cp0_sd_vccq";
60		regulator-min-microvolt = <1800000>;
61		regulator-max-microvolt = <3300000>;
62		gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
63		states = <1800000 0x1
64			  3300000 0x0>;
65	};
66
67	cp0_reg_sd_vcc: regulator-4 {
68		compatible = "regulator-fixed";
69		regulator-name = "cp0_sd_vcc";
70		regulator-min-microvolt = <3300000>;
71		regulator-max-microvolt = <3300000>;
72		gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
73		enable-active-high;
74		regulator-always-on;
75	};
76
77	sfp: sfp {
78		compatible = "sff,sfp";
79		i2c-bus = <&cp0_i2c1>;
80		mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
81		los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
82		tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
83		tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
84		maximum-power-milliwatt = <3000>;
85	};
86};
87
88&uart0 {
89	status = "okay";
90};
91
92/* on-board eMMC U6 */
93&ap_sdhci0 {
94	pinctrl-names = "default";
95	bus-width = <8>;
96	status = "okay";
97	mmc-ddr-1_8v;
98	vqmmc-supply = <&ap0_reg_mmc_vccq>;
99};
100
101&cp0_syscon0 {
102	cp0_pinctrl: pinctrl {
103		compatible = "marvell,cp115-standalone-pinctrl";
104
105		cp0_i2c0_pins: cp0-i2c-pins-0 {
106			marvell,pins = "mpp37", "mpp38";
107			marvell,function = "i2c0";
108		};
109		cp0_i2c1_pins: cp0-i2c-pins-1 {
110			marvell,pins = "mpp35", "mpp36";
111			marvell,function = "i2c1";
112		};
113		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
114			marvell,pins = "mpp55";
115			marvell,function = "gpio";
116		};
117		cp0_sdhci_pins: cp0-sdhi-pins-0 {
118			marvell,pins = "mpp56", "mpp57", "mpp58",
119				       "mpp59", "mpp60", "mpp61";
120			marvell,function = "sdio";
121		};
122		cp0_spi1_pins: cp0-spi-pins-1 {
123			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
124			marvell,function = "spi1";
125		};
126	};
127};
128
129&cp0_gpio1 {
130	status = "okay";
131};
132
133&cp0_gpio2 {
134	status = "okay";
135};
136
137&cp0_i2c0 {
138	pinctrl-names = "default";
139	pinctrl-0 = <&cp0_i2c0_pins>;
140	status = "okay";
141	clock-frequency = <100000>;
142	expander0: mcp23x17@20 {
143		compatible = "microchip,mcp23017";
144		gpio-controller;
145		#gpio-cells = <2>;
146		reg = <0x20>;
147		status = "okay";
148	};
149};
150
151&cp0_i2c1 {
152	pinctrl-names = "default";
153	pinctrl-0 = <&cp0_i2c1_pins>;
154	clock-frequency = <100000>;
155	status = "okay";
156};
157
158
159&cp0_sdhci0 {
160	pinctrl-names = "default";
161	pinctrl-0 = <&cp0_sdhci_pins
162		     &cp0_sdhci_cd_pins_crb>;
163	bus-width = <4>;
164	cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
165	vqmmc-supply = <&cp0_reg_sd_vccq>;
166	vmmc-supply = <&cp0_reg_sd_vcc>;
167	status = "okay";
168};
169
170&cp0_spi1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&cp0_spi1_pins>;
173	reg = <0x700680 0x50>,		/* control */
174	      <0x2000000 0x1000000>;	/* CS0 */
175	status = "okay";
176
177	flash@0 {
178		#address-cells = <0x1>;
179		#size-cells = <0x1>;
180		compatible = "jedec,spi-nor";
181		reg = <0x0>;
182		/* On-board MUX does not allow higher frequencies */
183		spi-max-frequency = <40000000>;
184
185		partitions {
186			compatible = "fixed-partitions";
187			#address-cells = <1>;
188			#size-cells = <1>;
189
190			partition@0 {
191				label = "U-Boot";
192				reg = <0x0 0x200000>;
193			};
194
195			partition@400000 {
196				label = "Filesystem";
197				reg = <0x200000 0xe00000>;
198			};
199		};
200	};
201};
202
203&cp0_mdio {
204	status = "okay";
205	phy0: ethernet-phy@0 {
206		reg = <0>;
207	};
208
209	switch6: ethernet-switch@6 {
210		/* Actual device is MV88E6393X */
211		compatible = "marvell,mv88e6190";
212		reg = <6>;
213		interrupt-parent = <&cp0_gpio1>;
214		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
215		interrupt-controller;
216		#interrupt-cells = <2>;
217
218		dsa,member = <0 0>;
219
220		ethernet-ports {
221			#address-cells = <1>;
222			#size-cells = <0>;
223
224			ethernet-port@1 {
225				reg = <1>;
226				label = "p1";
227				phy-handle = <&switch0phy1>;
228			};
229
230			ethernet-port@2 {
231				reg = <2>;
232				label = "p2";
233				phy-handle = <&switch0phy2>;
234			};
235
236			ethernet-port@3 {
237				reg = <3>;
238				label = "p3";
239				phy-handle = <&switch0phy3>;
240			};
241
242			ethernet-port@4 {
243				reg = <4>;
244				label = "p4";
245				phy-handle = <&switch0phy4>;
246			};
247
248			ethernet-port@5 {
249				reg = <5>;
250				label = "p5";
251				phy-handle = <&switch0phy5>;
252			};
253
254			ethernet-port@6 {
255				reg = <6>;
256				label = "p6";
257				phy-handle = <&switch0phy6>;
258			};
259
260			ethernet-port@7 {
261				reg = <7>;
262				label = "p7";
263				phy-handle = <&switch0phy7>;
264			};
265
266			ethernet-port@8 {
267				reg = <8>;
268				label = "p8";
269				phy-handle = <&switch0phy8>;
270			};
271
272			ethernet-port@9 {
273				reg = <9>;
274				label = "p9";
275				phy-mode = "10gbase-r";
276				sfp = <&sfp>;
277				managed = "in-band-status";
278			};
279
280			ethernet-port@a {
281				reg = <10>;
282				ethernet = <&cp0_eth0>;
283				phy-mode = "10gbase-r";
284				managed = "in-band-status";
285			};
286
287		};
288
289		mdio {
290			#address-cells = <1>;
291			#size-cells = <0>;
292
293			switch0phy1: ethernet-phy@1 {
294				reg = <0x1>;
295			};
296
297			switch0phy2: ethernet-phy@2 {
298				reg = <0x2>;
299			};
300
301			switch0phy3: ethernet-phy@3 {
302				reg = <0x3>;
303			};
304
305			switch0phy4: ethernet-phy@4 {
306				reg = <0x4>;
307			};
308
309			switch0phy5: ethernet-phy@5 {
310				reg = <0x5>;
311			};
312
313			switch0phy6: ethernet-phy@6 {
314				reg = <0x6>;
315			};
316
317			switch0phy7: ethernet-phy@7 {
318				reg = <0x7>;
319			};
320
321			switch0phy8: ethernet-phy@8 {
322				reg = <0x8>;
323			};
324		};
325	};
326};
327
328&cp0_xmdio {
329	status = "okay";
330	nbaset_phy0: ethernet-phy@0 {
331		compatible = "ethernet-phy-ieee802.3-c45";
332		reg = <0>;
333	};
334};
335
336&cp0_ethernet {
337	status = "okay";
338};
339
340&cp0_eth0 {
341	/* This port is connected to 88E6393X switch */
342	status = "okay";
343	phy-mode = "10gbase-r";
344	managed = "in-band-status";
345	phys = <&cp0_comphy4 0>;
346};
347
348&cp0_eth1 {
349	status = "okay";
350	phy = <&phy0>;
351	phy-mode = "rgmii-id";
352};
353
354&cp0_eth2 {
355	/* This port uses "2500base-t" phy-mode */
356	status = "disabled";
357	phy = <&nbaset_phy0>;
358	phys = <&cp0_comphy5 2>;
359};
360
361