1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP80x.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/dts-v1/;
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	aliases {
18		serial0 = &uart0;
19		serial1 = &uart1;
20		gpio0 = &ap_gpio;
21		spi0 = &spi0;
22	};
23
24	psci {
25		compatible = "arm,psci-0.2";
26		method = "smc";
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		/*
35		 * This area matches the mapping done with a
36		 * mainline U-Boot, and should be updated by the
37		 * bootloader.
38		 */
39
40		psci-area@4000000 {
41			reg = <0x0 0x4000000 0x0 0x200000>;
42			no-map;
43		};
44
45		tee@4400000 {
46			reg = <0 0x4400000 0 0x1000000>;
47			no-map;
48		};
49	};
50
51	AP_NAME {
52		#address-cells = <2>;
53		#size-cells = <2>;
54		compatible = "simple-bus";
55		interrupt-parent = <&gic>;
56		ranges;
57
58		config-space@f0000000 {
59			#address-cells = <1>;
60			#size-cells = <1>;
61			compatible = "simple-bus";
62			ranges = <0x0 0x0 0xf0000000 0x1000000>;
63
64			smmu: iommu@100000 {
65				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
66				reg = <0x100000 0x100000>;
67				dma-coherent;
68				#iommu-cells = <1>;
69				#global-interrupts = <1>;
70				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
74					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
75					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
76					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
77					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79				status = "disabled";
80			};
81
82			gic: interrupt-controller@210000 {
83				compatible = "arm,gic-400";
84				#interrupt-cells = <3>;
85				#address-cells = <1>;
86				#size-cells = <1>;
87				ranges;
88				interrupt-controller;
89				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90				reg = <0x210000 0x10000>,
91				      <0x220000 0x20000>,
92				      <0x240000 0x20000>,
93				      <0x260000 0x20000>;
94
95				gic_v2m0: v2m@280000 {
96					compatible = "arm,gic-v2m-frame";
97					msi-controller;
98					reg = <0x280000 0x1000>;
99					arm,msi-base-spi = <160>;
100					arm,msi-num-spis = <32>;
101				};
102				gic_v2m1: v2m@290000 {
103					compatible = "arm,gic-v2m-frame";
104					msi-controller;
105					reg = <0x290000 0x1000>;
106					arm,msi-base-spi = <192>;
107					arm,msi-num-spis = <32>;
108				};
109				gic_v2m2: v2m@2a0000 {
110					compatible = "arm,gic-v2m-frame";
111					msi-controller;
112					reg = <0x2a0000 0x1000>;
113					arm,msi-base-spi = <224>;
114					arm,msi-num-spis = <32>;
115				};
116				gic_v2m3: v2m@2b0000 {
117					compatible = "arm,gic-v2m-frame";
118					msi-controller;
119					reg = <0x2b0000 0x1000>;
120					arm,msi-base-spi = <256>;
121					arm,msi-num-spis = <32>;
122				};
123			};
124
125			timer {
126				compatible = "arm,armv8-timer";
127				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
130					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
131			};
132
133			pmu {
134				compatible = "arm,cortex-a72-pmu";
135				interrupt-parent = <&pic>;
136				interrupts = <17>;
137			};
138
139			odmi: odmi@300000 {
140				compatible = "marvell,odmi-controller";
141				msi-controller;
142				marvell,odmi-frames = <4>;
143				reg = <0x300000 0x4000>,
144				      <0x304000 0x4000>,
145				      <0x308000 0x4000>,
146				      <0x30C000 0x4000>;
147				marvell,spi-base = <128>, <136>, <144>, <152>;
148			};
149
150			gicp: gicp@3f0040 {
151				compatible = "marvell,ap806-gicp";
152				reg = <0x3f0040 0x10>;
153				marvell,spi-ranges = <64 64>, <288 64>;
154				msi-controller;
155			};
156
157			pic: interrupt-controller@3f0100 {
158				compatible = "marvell,armada-8k-pic";
159				reg = <0x3f0100 0x10>;
160				#interrupt-cells = <1>;
161				interrupt-controller;
162				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
163			};
164
165			sei: interrupt-controller@3f0200 {
166				compatible = "marvell,ap806-sei";
167				reg = <0x3f0200 0x40>;
168				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
169				#interrupt-cells = <1>;
170				interrupt-controller;
171				msi-controller;
172			};
173
174			xor@400000 {
175				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
176				reg = <0x400000 0x1000>,
177				      <0x410000 0x1000>;
178				msi-parent = <&gic_v2m0>;
179				clocks = <&ap_clk 3>;
180				dma-coherent;
181			};
182
183			xor@420000 {
184				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
185				reg = <0x420000 0x1000>,
186				      <0x430000 0x1000>;
187				msi-parent = <&gic_v2m0>;
188				clocks = <&ap_clk 3>;
189				dma-coherent;
190			};
191
192			xor@440000 {
193				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
194				reg = <0x440000 0x1000>,
195				      <0x450000 0x1000>;
196				msi-parent = <&gic_v2m0>;
197				clocks = <&ap_clk 3>;
198				dma-coherent;
199			};
200
201			xor@460000 {
202				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
203				reg = <0x460000 0x1000>,
204				      <0x470000 0x1000>;
205				msi-parent = <&gic_v2m0>;
206				clocks = <&ap_clk 3>;
207				dma-coherent;
208			};
209
210			spi0: spi@510600 {
211				compatible = "marvell,armada-380-spi";
212				reg = <0x510600 0x50>;
213				#address-cells = <1>;
214				#size-cells = <0>;
215				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
216				clocks = <&ap_clk 3>;
217				status = "disabled";
218			};
219
220			i2c0: i2c@511000 {
221				compatible = "marvell,mv78230-i2c";
222				reg = <0x511000 0x20>;
223				#address-cells = <1>;
224				#size-cells = <0>;
225				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
226				clocks = <&ap_clk 3>;
227				status = "disabled";
228			};
229
230			uart0: serial@512000 {
231				compatible = "snps,dw-apb-uart";
232				reg = <0x512000 0x100>;
233				reg-shift = <2>;
234				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
235				reg-io-width = <1>;
236				clocks = <&ap_clk 3>;
237				status = "disabled";
238			};
239
240			uart1: serial@512100 {
241				compatible = "snps,dw-apb-uart";
242				reg = <0x512100 0x100>;
243				reg-shift = <2>;
244				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245				reg-io-width = <1>;
246				clocks = <&ap_clk 3>;
247				status = "disabled";
248
249			};
250
251			watchdog: watchdog@610000 {
252				compatible = "arm,sbsa-gwdt";
253				reg = <0x610000 0x1000>, <0x600000 0x1000>;
254				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
255			};
256
257			ap_sdhci0: mmc@6e0000 {
258				compatible = "marvell,armada-ap806-sdhci";
259				reg = <0x6e0000 0x300>;
260				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
261				clock-names = "core";
262				clocks = <&ap_clk 4>;
263				dma-coherent;
264				marvell,xenon-phy-slow-mode;
265				status = "disabled";
266			};
267
268			ap_syscon0: system-controller@6f4000 {
269				compatible = "syscon", "simple-mfd";
270				reg = <0x6f4000 0x2000>;
271
272				ap_pinctrl: pinctrl {
273					compatible = "marvell,ap806-pinctrl";
274
275					uart0_pins: uart0-pins {
276						marvell,pins = "mpp11", "mpp19";
277						marvell,function = "uart0";
278					};
279				};
280
281				ap_gpio: gpio@1040 {
282					compatible = "marvell,armada-8k-gpio";
283					offset = <0x1040>;
284					ngpios = <20>;
285					gpio-controller;
286					#gpio-cells = <2>;
287					gpio-ranges = <&ap_pinctrl 0 0 20>;
288					marvell,pwm-offset = <0x10c0>;
289					#pwm-cells = <2>;
290					clocks = <&ap_clk 3>;
291				};
292			};
293
294			ap_syscon1: system-controller@6f8000 {
295				compatible = "syscon", "simple-mfd";
296				reg = <0x6f8000 0x1000>;
297				#address-cells = <1>;
298				#size-cells = <1>;
299
300				ap_thermal: thermal-sensor@80 {
301					compatible = "marvell,armada-ap806-thermal";
302					reg = <0x80 0x10>;
303					interrupt-parent = <&sei>;
304					interrupts = <18>;
305					#thermal-sensor-cells = <1>;
306				};
307			};
308		};
309	};
310
311	/*
312	 * The thermal IP features one internal sensor plus, if applicable, one
313	 * remote channel wired to one sensor per CPU.
314	 *
315	 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
316	 * first one that will have a critical trip point will be chosen.
317	 */
318	thermal-zones {
319		ap_thermal_ic: ap-ic-thermal {
320			polling-delay-passive = <0>; /* Interrupt driven */
321			polling-delay = <0>; /* Interrupt driven */
322
323			thermal-sensors = <&ap_thermal 0>;
324
325			trips {
326				ap_crit: ap-crit {
327					temperature = <100000>; /* mC degrees */
328					hysteresis = <2000>; /* mC degrees */
329					type = "critical";
330				};
331			};
332
333			cooling-maps { };
334		};
335
336		ap_thermal_cpu0: ap-cpu0-thermal {
337			polling-delay-passive = <1000>;
338			polling-delay = <1000>;
339
340			thermal-sensors = <&ap_thermal 1>;
341
342			trips {
343				cpu0_hot: cpu0-hot {
344					temperature = <85000>;
345					hysteresis = <2000>;
346					type = "passive";
347				};
348				cpu0_emerg: cpu0-emerg {
349					temperature = <95000>;
350					hysteresis = <2000>;
351					type = "passive";
352				};
353			};
354
355			cooling-maps {
356				map0_hot: map0-hot {
357					trip = <&cpu0_hot>;
358					cooling-device = <&cpu0 1 2>,
359						<&cpu1 1 2>;
360				};
361				map0_emerg: map0-ermerg {
362					trip = <&cpu0_emerg>;
363					cooling-device = <&cpu0 3 3>,
364						<&cpu1 3 3>;
365				};
366			};
367		};
368
369		ap_thermal_cpu1: ap-cpu1-thermal {
370			polling-delay-passive = <1000>;
371			polling-delay = <1000>;
372
373			thermal-sensors = <&ap_thermal 2>;
374
375			trips {
376				cpu1_hot: cpu1-hot {
377					temperature = <85000>;
378					hysteresis = <2000>;
379					type = "passive";
380				};
381				cpu1_emerg: cpu1-emerg {
382					temperature = <95000>;
383					hysteresis = <2000>;
384					type = "passive";
385				};
386			};
387
388			cooling-maps {
389				map1_hot: map1-hot {
390					trip = <&cpu1_hot>;
391					cooling-device = <&cpu0 1 2>,
392						<&cpu1 1 2>;
393				};
394				map1_emerg: map1-emerg {
395					trip = <&cpu1_emerg>;
396					cooling-device = <&cpu0 3 3>,
397						<&cpu1 3 3>;
398				};
399			};
400		};
401
402		ap_thermal_cpu2: ap-cpu2-thermal {
403			polling-delay-passive = <1000>;
404			polling-delay = <1000>;
405
406			thermal-sensors = <&ap_thermal 3>;
407
408			trips {
409				cpu2_hot: cpu2-hot {
410					temperature = <85000>;
411					hysteresis = <2000>;
412					type = "passive";
413				};
414				cpu2_emerg: cpu2-emerg {
415					temperature = <95000>;
416					hysteresis = <2000>;
417					type = "passive";
418				};
419			};
420
421			cooling-maps {
422				map2_hot: map2-hot {
423					trip = <&cpu2_hot>;
424					cooling-device = <&cpu2 1 2>,
425						<&cpu3 1 2>;
426				};
427				map2_emerg: map2-emerg {
428					trip = <&cpu2_emerg>;
429					cooling-device = <&cpu2 3 3>,
430						<&cpu3 3 3>;
431				};
432			};
433		};
434
435		ap_thermal_cpu3: ap-cpu3-thermal {
436			polling-delay-passive = <1000>;
437			polling-delay = <1000>;
438
439			thermal-sensors = <&ap_thermal 4>;
440
441			trips {
442				cpu3_hot: cpu3-hot {
443					temperature = <85000>;
444					hysteresis = <2000>;
445					type = "passive";
446				};
447				cpu3_emerg: cpu3-emerg {
448					temperature = <95000>;
449					hysteresis = <2000>;
450					type = "passive";
451				};
452			};
453
454			cooling-maps {
455				map3_hot: map3-bhot {
456					trip = <&cpu3_hot>;
457					cooling-device = <&cpu2 1 2>,
458						<&cpu3 1 2>;
459				};
460				map3_emerg: map3-emerg {
461					trip = <&cpu3_emerg>;
462					cooling-device = <&cpu2 3 3>,
463						<&cpu3 3 3>;
464				};
465			};
466		};
467	};
468};
469