1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 Avnet Embedded GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9#include <dt-bindings/net/ti-dp83867.h>
10
11/ {
12	aliases {
13		rtc0 = &sys_rtc;
14		rtc1 = &snvs_rtc;
15	};
16
17	chosen {
18		stdout-path = &uart2;
19	};
20
21	reg_usb0_host_vbus: regulator-usb0-vbus {
22		compatible = "regulator-fixed";
23		regulator-name = "usb0_host_vbus";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_usb0_vbus>;
26		regulator-min-microvolt = <5000000>;
27		regulator-max-microvolt = <5000000>;
28		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31
32	reg_usb1_host_vbus: regulator-usb1-vbus {
33		compatible = "regulator-fixed";
34		regulator-name = "usb1_host_vbus";
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_usb1_vbus>;
37		regulator-min-microvolt = <5000000>;
38		regulator-max-microvolt = <5000000>;
39		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41	};
42
43	reg_usdhc2_vmmc: regulator-usdhc2 {
44		compatible = "regulator-fixed";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
47		regulator-name = "VSD_3V3";
48		regulator-min-microvolt = <3300000>;
49		regulator-max-microvolt = <3300000>;
50		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51		enable-active-high;
52		startup-delay-us = <100>;
53		off-on-delay-us = <12000>;
54	};
55
56	reg_flexcan1_xceiver: regulator-flexcan1 {
57		compatible = "regulator-fixed";
58		regulator-name = "flexcan1-xceiver";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61	};
62
63	reg_flexcan2_xceiver: regulator-flexcan2 {
64		compatible = "regulator-fixed";
65		regulator-name = "flexcan2-xceiver";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68	};
69
70	lcd0_backlight: backlight-0 {
71		compatible = "pwm-backlight";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_lcd0_backlight>;
74		pwms = <&pwm1 0 100000 0>;
75		brightness-levels = <0 255>;
76		num-interpolated-steps = <255>;
77		default-brightness-level = <255>;
78		enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
79		status = "disabled";
80	};
81
82	lcd1_backlight: backlight-1 {
83		compatible = "pwm-backlight";
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_lcd1_backlight>;
86		pwms = <&pwm2 0 100000 0>;
87		brightness-levels = <0 255>;
88		num-interpolated-steps = <255>;
89		default-brightness-level = <255>;
90		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
91		status = "disabled";
92	};
93
94	leds {
95		compatible = "gpio-leds";
96		pinctrl-names = "default";
97		pinctrl-0 = <&pinctrl_leds>;
98		status = "okay";
99
100		led-sw {
101			label = "sw-led";
102			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
103			default-state = "off";
104			linux,default-trigger = "heartbeat";
105		};
106	};
107
108	extcon_usb0: extcon-usb0 {
109		compatible = "linux,extcon-usb-gpio";
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_usb0_extcon>;
112		id-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
113	};
114};
115
116&A53_0 {
117	cpu-supply = <&vcc_arm>;
118};
119
120&A53_1 {
121	cpu-supply = <&vcc_arm>;
122};
123
124&A53_2 {
125	cpu-supply = <&vcc_arm>;
126};
127
128&A53_3 {
129	cpu-supply = <&vcc_arm>;
130};
131
132&ecspi1 {
133	#address-cells = <1>;
134	#size-cells = <0>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_ecspi1>;
137	cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
138};
139
140&ecspi2 {
141	#address-cells = <1>;
142	#size-cells = <0>;
143	pinctrl-names = "default";
144	pinctrl-0 = <&pinctrl_ecspi2>;
145	cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
146};
147
148&eqos {
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_eqos>;
151	phy-mode = "rgmii-id";
152	phy-handle = <&ethphy0>;
153	status = "okay";
154
155	mdio {
156		compatible = "snps,dwmac-mdio";
157		#address-cells = <1>;
158		#size-cells = <0>;
159
160		ethphy0: ethernet-phy@1 {
161			compatible = "ethernet-phy-ieee802.3-c22";
162			reg = <1>;
163			eee-broken-1000t;
164			reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
165			reset-assert-us = <1000>;
166			reset-deassert-us = <1000>;
167			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
168			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
169			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
170			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
171		};
172	};
173};
174
175&fec {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_fec>;
178	phy-mode = "rgmii-id";
179	phy-handle = <&ethphy1>;
180	fsl,magic-packet;
181	status = "okay";
182
183	mdio {
184		#address-cells = <1>;
185		#size-cells = <0>;
186
187		ethphy1: ethernet-phy@1 {
188			compatible = "ethernet-phy-ieee802.3-c22";
189			reg = <1>;
190			eee-broken-1000t;
191			reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
192			reset-assert-us = <1000>;
193			reset-deassert-us = <1000>;
194			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
195			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
196			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
197			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
198		};
199	};
200};
201
202&i2c1 {
203	pinctrl-names = "default", "gpio";
204	pinctrl-0 = <&pinctrl_i2c1>;
205	pinctrl-1 = <&pinctrl_i2c1_gpio>;
206	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
207	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
208	clock-frequency = <400000>;
209	status = "okay";
210
211	id_eeprom: eeprom@50 {
212		compatible = "atmel,24c64";
213		reg = <0x50>;
214		pagesize = <32>;
215	};
216};
217
218&i2c2 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_i2c2>;
221	clock-frequency = <400000>;
222	status = "disabled";
223};
224
225&i2c3 {
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_i2c3>;
228	clock-frequency = <400000>;
229	status = "disabled";
230};
231
232&i2c4 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_i2c4>;
235	clock-frequency = <400000>;
236	status = "disabled";
237};
238
239&i2c5 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_i2c5>;
242	clock-frequency = <400000>;
243	status = "disabled";
244};
245
246&i2c6 {
247	pinctrl-names = "default", "gpio";
248	pinctrl-0 = <&pinctrl_i2c6>;
249	pinctrl-1 = <&pinctrl_i2c6_gpio>;
250	scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
251	sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
252	clock-frequency = <400000>;
253	status = "okay";
254
255	tca6424: gpio@22 {
256		compatible = "ti,tca6424";
257		reg = <0x22>;
258		pinctrl-names = "default";
259		pinctrl-0 = <&pinctrl_tca6424>;
260		gpio-controller;
261		#gpio-cells = <2>;
262		gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
263			"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
264			"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
265			"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
266			"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
267			"CHARGER_PRSNT#";
268		interrupt-parent = <&gpio1>;
269		interrupts = <9 IRQ_TYPE_EDGE_RISING>;
270		interrupt-controller;
271		#interrupt-cells = <2>;
272	};
273
274	dsi_lvds_bridge: bridge@2d {
275		compatible = "ti,sn65dsi83";
276		reg = <0x2d>;
277		pinctrl-names = "default";
278		pinctrl-0 = <&pinctrl_lvds_bridge>;
279		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
280		status = "disabled";
281	};
282
283	pmic: pmic@30 {
284		compatible = "ricoh,rn5t567";
285		reg = <0x30>;
286		interrupt-parent = <&tca6424>;
287		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
288
289		regulators {
290			DCDC1 {
291				regulator-name = "VCC_SOC";
292				regulator-always-on;
293				regulator-min-microvolt = <950000>;
294				regulator-max-microvolt = <950000>;
295			};
296
297			DCDC2 {
298				regulator-name = "VCC_DRAM";
299				regulator-always-on;
300				regulator-min-microvolt = <1100000>;
301				regulator-max-microvolt = <1100000>;
302			};
303
304			vcc_arm: DCDC3 {
305				regulator-name = "VCC_ARM";
306				regulator-always-on;
307				regulator-min-microvolt = <950000>;
308				regulator-max-microvolt = <950000>;
309			};
310
311			DCDC4 {
312				regulator-name = "VCC_1V8";
313				regulator-always-on;
314				regulator-min-microvolt = <1800000>;
315				regulator-max-microvolt = <1800000>;
316			};
317
318			LDO1 {
319				regulator-name = "VCC_LDO1_2V5";
320				regulator-always-on;
321				regulator-min-microvolt = <2500000>;
322				regulator-max-microvolt = <2500000>;
323			};
324
325			LDO2 {
326				regulator-name = "VCC_LDO2_1V8";
327				regulator-always-on;
328				regulator-min-microvolt = <1800000>;
329				regulator-max-microvolt = <1800000>;
330			};
331
332			LDO3 {
333				regulator-name = "VCC_ETH_2V5";
334				regulator-always-on;
335				regulator-min-microvolt = <2500000>;
336				regulator-max-microvolt = <2500000>;
337			};
338
339			LDO4 {
340				regulator-name = "VCC_DDR4_2V5";
341				regulator-always-on;
342				regulator-min-microvolt = <2500000>;
343				regulator-max-microvolt = <2500000>;
344			};
345
346			LDO5 {
347				regulator-name = "VCC_LDO5_1V8";
348				regulator-always-on;
349				regulator-min-microvolt = <1800000>;
350				regulator-max-microvolt = <1800000>;
351			};
352
353			LDORTC1 {
354				regulator-name = "VCC_SNVS_1V8";
355				regulator-always-on;
356				regulator-min-microvolt = <1800000>;
357				regulator-max-microvolt = <1800000>;
358			};
359
360			LDORTC2 {
361				regulator-name = "VCC_SNVS_3V3";
362				regulator-always-on;
363				regulator-min-microvolt = <3300000>;
364				regulator-max-microvolt = <3300000>;
365			};
366		};
367	};
368
369	sys_rtc: rtc@32 {
370		compatible = "ricoh,r2221tl";
371		reg = <0x32>;
372		interrupt-parent = <&tca6424>;
373		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
374	};
375
376	tmp_sensor: temperature-sensor@71 {
377		compatible = "ti,tmp103";
378		reg = <0x71>;
379	};
380};
381
382&flexcan1 {
383	pinctrl-names = "default";
384	pinctrl-0 = <&pinctrl_flexcan1>;
385	xceiver-supply = <&reg_flexcan1_xceiver>;
386	status = "disabled";
387};
388
389&flexcan2 {
390	pinctrl-names = "default";
391	pinctrl-0 = <&pinctrl_flexcan2>;
392	xceiver-supply = <&reg_flexcan2_xceiver>;
393	status = "disabled";
394};
395
396&flexspi {
397	pinctrl-names = "default";
398	pinctrl-0 = <&pinctrl_flexspi0>;
399	status = "okay";
400
401	qspi_flash: flash@0 {
402		compatible = "jedec,spi-nor";
403		reg = <0>;
404		#address-cells = <1>;
405		#size-cells = <1>;
406		spi-max-frequency = <80000000>;
407		spi-tx-bus-width = <4>;
408		spi-rx-bus-width = <4>;
409	};
410};
411
412&pwm1 {
413	pinctrl-names = "default";
414	pinctrl-0 = <&pinctrl_pwm1>;
415	status = "disabled";
416};
417
418&pwm2 {
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_pwm2>;
421	status = "disabled";
422};
423
424&pwm3 {
425	pinctrl-names = "default";
426	pinctrl-0 = <&pinctrl_pwm3>;
427	status = "disabled";
428};
429
430&pwm4 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&pinctrl_pwm4>;
433	status = "disabled";
434};
435
436&snvs_pwrkey {
437	status = "okay";
438};
439
440&uart1 {
441	pinctrl-names = "default";
442	pinctrl-0 = <&pinctrl_uart1>;
443	status = "okay";
444};
445
446&uart2 {
447	pinctrl-names = "default";
448	pinctrl-0 = <&pinctrl_uart2>;
449	uart-has-rtscts;
450	status = "okay";
451};
452
453&uart3 {
454	pinctrl-names = "default";
455	pinctrl-0 = <&pinctrl_uart3>;
456	uart-has-rtscts;
457	status = "okay";
458};
459
460&uart4 {
461	pinctrl-names = "default";
462	pinctrl-0 = <&pinctrl_uart4>;
463	status = "disabled";
464};
465
466&usb3_phy0 {
467	vbus-supply = <&reg_usb0_host_vbus>;
468	status = "okay";
469};
470
471&usb3_phy1 {
472	vbus-supply = <&reg_usb1_host_vbus>;
473	status = "okay";
474};
475
476&usb3_0 {
477	status = "okay";
478};
479
480&usb3_1 {
481	status = "okay";
482};
483
484&usb_dwc3_0 {
485	dr_mode = "otg";
486	hnp-disable;
487	srp-disable;
488	adp-disable;
489	extcon = <&extcon_usb0>;
490	status = "okay";
491};
492
493&usb_dwc3_1 {
494	dr_mode = "host";
495	status = "okay";
496};
497
498&usdhc2 {
499	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
500	assigned-clock-rates = <400000000>;
501	pinctrl-names = "default", "state_100mhz", "state_200mhz";
502	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
503	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
504	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
505	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
506	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
507	bus-width = <4>;
508	vmmc-supply = <&reg_usdhc2_vmmc>;
509	status = "okay";
510};
511
512&usdhc3 {
513	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
514	assigned-clock-rates = <400000000>;
515	pinctrl-names = "default", "state_100mhz", "state_200mhz";
516	pinctrl-0 = <&pinctrl_usdhc3>;
517	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
518	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
519	bus-width = <8>;
520	non-removable;
521	status = "okay";
522};
523
524&wdog1 {
525	pinctrl-names = "default";
526	pinctrl-0 = <&pinctrl_wdog>;
527	fsl,ext-reset-output;
528	status = "okay";
529};
530
531&iomuxc {
532	pinctrl_ecspi1: ecspi1grp {
533		fsl,pins =
534			<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82>,
535			<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82>,
536			<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82>,
537			<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0		0x40000>,
538			<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x40000>;
539	};
540
541	pinctrl_ecspi2: ecspi2grp {
542		fsl,pins =
543			<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82>,
544			<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82>,
545			<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82>,
546			<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000>,
547			<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x40000>;
548	};
549
550	pinctrl_eqos: eqosgrp {
551		fsl,pins =
552			<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3>,
553			<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3>,
554			<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91>,
555			<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91>,
556			<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91>,
557			<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91>,
558			<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91>,
559			<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91>,
560			<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f>,
561			<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f>,
562			<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f>,
563			<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f>,
564			<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f>,
565			<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f>;
566	};
567
568	pinctrl_fec: fecgrp {
569		fsl,pins =
570			<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3>,
571			<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3>,
572			<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91>,
573			<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91>,
574			<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91>,
575			<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91>,
576			<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91>,
577			<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91>,
578			<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f>,
579			<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f>,
580			<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f>,
581			<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f>,
582			<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f>,
583			<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f>;
584	};
585
586	pinctrl_flexcan1: flexcan1grp {
587		fsl,pins =
588			<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154>,
589			<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154>;
590	};
591
592	pinctrl_flexcan2: flexcan2grp {
593		fsl,pins =
594			<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154>,
595			<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154>;
596	};
597
598	pinctrl_flexspi0: flexspi0grp {
599		fsl,pins =
600			<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2>,
601			<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
602			<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
603			<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
604			<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
605			<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>,
606			<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x19>;
607	};
608
609	pinctrl_i2c1: i2c1grp {
610		fsl,pins =
611			<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e0>,
612			<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e0>;
613	};
614
615	pinctrl_i2c1_gpio: i2c1gpiogrp {
616		fsl,pins =
617			<MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x1e0>,
618			<MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x1e0>;
619	};
620
621	pinctrl_i2c2: i2c2grp {
622		fsl,pins =
623			<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001e0>,
624			<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001e0>;
625	};
626
627	pinctrl_i2c3: i2c3grp {
628		fsl,pins =
629			<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001e0>,
630			<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001e0>;
631	};
632
633	pinctrl_i2c4: i2c4grp {
634		fsl,pins =
635			<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001e0>,
636			<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001e0>;
637	};
638
639	pinctrl_i2c5: i2c5grp {
640		fsl,pins =
641			<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001e0>,
642			<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001e0>;
643	};
644
645	pinctrl_i2c6: i2c6grp {
646		fsl,pins =
647			<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001e0>,
648			<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001e0>;
649	};
650
651	pinctrl_i2c6_gpio: i2c6gpiogrp {
652		fsl,pins =
653			<MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x1e0>,
654			<MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x1e0>;
655	};
656
657	pinctrl_lcd0_backlight: lcd0-backlightgrp {
658		fsl,pins =
659			<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x41>;
660	};
661
662	pinctrl_lcd1_backlight: lcd1-backlightgrp {
663		fsl,pins =
664			<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x41>;
665	};
666
667	pinctrl_leds: ledsgrp {
668		fsl,pins =
669			<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x19>;
670	};
671
672	pinctrl_lvds_bridge: lvds-bridgegrp {
673		fsl,pins =
674			<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x41>;
675	};
676
677	pinctrl_pwm1: pwm1grp {
678		fsl,pins =
679			<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116>;
680	};
681
682	pinctrl_pwm2: pwm2grp {
683		fsl,pins =
684			<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116>;
685	};
686
687	pinctrl_pwm3: pwm3grp {
688		fsl,pins =
689			<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT		0x116>;
690	};
691
692	pinctrl_pwm4: pwm4grp {
693		fsl,pins =
694			<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116>;
695	};
696
697	pinctrl_tca6424: tca6424grp {
698		fsl,pins =
699			<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x41>;
700	};
701
702	pinctrl_uart1: uart1grp {
703		fsl,pins =
704			<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49>,
705			<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49>;
706	};
707
708	pinctrl_uart2: uart2grp {
709		fsl,pins =
710			<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x1c4>,
711			<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x1c4>,
712			<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49>,
713			<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49>;
714	};
715
716	pinctrl_uart3: uart3grp {
717		fsl,pins =
718			<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4>,
719			<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x1c4>,
720			<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49>,
721			<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49>;
722	};
723
724	pinctrl_uart4: uart4grp {
725		fsl,pins =
726			<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49>,
727			<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49>;
728	};
729
730	pinctrl_usb0_extcon: usb0-extcongrp {
731		fsl,pins =
732			<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x19>;
733	};
734
735	pinctrl_usb0_vbus: usb0-vbusgrp {
736		fsl,pins =
737			<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x19>;
738	};
739
740	pinctrl_usb1_vbus: usb1-vbusgrp {
741		fsl,pins =
742			<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x19>;
743	};
744
745	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
746		fsl,pins =
747			<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4>,
748			<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x1c4>;
749	};
750
751	pinctrl_usdhc2: usdhc2grp {
752		fsl,pins =
753			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190>,
754			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0>,
755			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0>,
756			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0>,
757			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0>,
758			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0>,
759			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
760	};
761
762	pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
763		fsl,pins =
764			<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41>;
765	};
766
767	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
768		fsl,pins =
769			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
770			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
771			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4>,
772			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4>,
773			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4>,
774			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4>,
775			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
776	};
777
778	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
779		fsl,pins =
780			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196>,
781			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6>,
782			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6>,
783			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6>,
784			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6>,
785			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6>,
786			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
787	};
788
789	pinctrl_usdhc3: usdhc3grp {
790		fsl,pins =
791			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190>,
792			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0>,
793			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0>,
794			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0>,
795			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0>,
796			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0>,
797			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0>,
798			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0>,
799			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0>,
800			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0>,
801			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190>;
802	};
803
804	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
805		fsl,pins =
806			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
807			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
808			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4>,
809			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4>,
810			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4>,
811			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4>,
812			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4>,
813			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4>,
814			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4>,
815			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
816			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194>;
817	};
818
819	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
820		fsl,pins =
821			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196>,
822			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6>,
823			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6>,
824			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6>,
825			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6>,
826			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6>,
827			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6>,
828			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6>,
829			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6>,
830			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6>,
831			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196>;
832	};
833
834	pinctrl_wdog: wdoggrp {
835		fsl,pins =
836			<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6>;
837	};
838};
839