1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/clock/g12a-clkc.h>
10#include "meson-g12b-a311d.dtsi"
11#include "meson-libretech-cottonwood.dtsi"
12
13/ {
14	compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";
15	model = "Libre Computer AML-A311D-CC Alta";
16
17	vddcpu_a: regulator-vddcpu-a {
18		compatible = "pwm-regulator";
19		regulator-name = "VDDCPU_A";
20		regulator-min-microvolt = <730000>;
21		regulator-max-microvolt = <1011000>;
22		regulator-boot-on;
23		regulator-always-on;
24		pwm-supply = <&dc_in>;
25		pwms = <&pwm_ab 0 1250 0>;
26		pwm-dutycycle-range = <100 0>;
27	};
28
29	sound {
30		model = "LC-ALTA";
31		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
32				"TDMOUT_A IN 1", "FRDDR_B OUT 0",
33				"TDMOUT_A IN 2", "FRDDR_C OUT 0",
34				"TDM_A Playback", "TDMOUT_A OUT",
35				"TDMOUT_B IN 0", "FRDDR_A OUT 1",
36				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
37				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
38				"TDM_B Playback", "TDMOUT_B OUT",
39				"TDMOUT_C IN 0", "FRDDR_A OUT 2",
40				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
41				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
42				"TDM_C Playback", "TDMOUT_C OUT",
43				"TDMIN_A IN 0", "TDM_A Capture",
44				"TDMIN_B IN 0", "TDM_A Capture",
45				"TDMIN_C IN 0", "TDM_A Capture",
46				"TDMIN_A IN 3", "TDM_A Loopback",
47				"TDMIN_B IN 3", "TDM_A Loopback",
48				"TDMIN_C IN 3", "TDM_A Loopback",
49				"TDMIN_A IN 1", "TDM_B Capture",
50				"TDMIN_B IN 1", "TDM_B Capture",
51				"TDMIN_C IN 1", "TDM_B Capture",
52				"TDMIN_A IN 4", "TDM_B Loopback",
53				"TDMIN_B IN 4", "TDM_B Loopback",
54				"TDMIN_C IN 4", "TDM_B Loopback",
55				"TDMIN_A IN 2", "TDM_C Capture",
56				"TDMIN_B IN 2", "TDM_C Capture",
57				"TDMIN_C IN 2", "TDM_C Capture",
58				"TDMIN_A IN 5", "TDM_C Loopback",
59				"TDMIN_B IN 5", "TDM_C Loopback",
60				"TDMIN_C IN 5", "TDM_C Loopback",
61				"TODDR_A IN 0", "TDMIN_A OUT",
62				"TODDR_B IN 0", "TDMIN_A OUT",
63				"TODDR_C IN 0", "TDMIN_A OUT",
64				"TODDR_A IN 1", "TDMIN_B OUT",
65				"TODDR_B IN 1", "TDMIN_B OUT",
66				"TODDR_C IN 1", "TDMIN_B OUT",
67				"TODDR_A IN 2", "TDMIN_C OUT",
68				"TODDR_B IN 2", "TDMIN_C OUT",
69				"TODDR_C IN 2", "TDMIN_C OUT",
70				"Lineout", "ACODEC LOLP",
71				"Lineout", "ACODEC LORP";
72	};
73};
74
75&cpu0 {
76	cpu-supply = <&vddcpu_b>;
77	operating-points-v2 = <&cpu_opp_table_0>;
78	clocks = <&clkc CLKID_CPU_CLK>;
79	clock-latency = <50000>;
80};
81
82&cpu1 {
83	cpu-supply = <&vddcpu_b>;
84	operating-points-v2 = <&cpu_opp_table_0>;
85	clocks = <&clkc CLKID_CPU_CLK>;
86	clock-latency = <50000>;
87};
88
89&cpu100 {
90	cpu-supply = <&vddcpu_a>;
91	operating-points-v2 = <&cpub_opp_table_1>;
92	clocks = <&clkc CLKID_CPUB_CLK>;
93	clock-latency = <50000>;
94};
95
96&cpu101 {
97	cpu-supply = <&vddcpu_a>;
98	operating-points-v2 = <&cpub_opp_table_1>;
99	clocks = <&clkc CLKID_CPUB_CLK>;
100	clock-latency = <50000>;
101};
102
103&cpu102 {
104	cpu-supply = <&vddcpu_a>;
105	operating-points-v2 = <&cpub_opp_table_1>;
106	clocks = <&clkc CLKID_CPUB_CLK>;
107	clock-latency = <50000>;
108};
109
110&cpu103 {
111	cpu-supply = <&vddcpu_a>;
112	operating-points-v2 = <&cpub_opp_table_1>;
113	clocks = <&clkc CLKID_CPUB_CLK>;
114	clock-latency = <50000>;
115};
116
117&pwm_ab {
118	pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x7_pins>;
119	clocks = <&xtal>, <&xtal>;
120	clock-names = "clkin0", "clkin1";
121};
122