1259701Sdim/* SPDX-License-Identifier: GPL-2.0 */ 2259701Sdim/* 3259701Sdim * Copyright 2008 Openmoko, Inc. 4259701Sdim * Copyright 2008 Simtec Electronics 5259701Sdim * http://armlinux.simtec.co.uk/ 6259701Sdim * Ben Dooks <ben@simtec.co.uk> 7259701Sdim * 8259701Sdim * S3C64XX - Memory map definitions 9259701Sdim */ 10259701Sdim 11259701Sdim#ifndef __ASM_ARCH_MAP_H 12259701Sdim#define __ASM_ARCH_MAP_H __FILE__ 13259701Sdim 14259701Sdim#include "map-base.h" 15259701Sdim#include "map-s3c.h" 16259701Sdim 17259701Sdim/* 18259701Sdim * Post-mux Chip Select Regions Xm0CSn_ 19259701Sdim * These may be used by SROM, NAND or CF depending on settings 20259701Sdim */ 21259701Sdim 22259701Sdim#define S3C64XX_PA_XM0CSN0 (0x10000000) 23259701Sdim#define S3C64XX_PA_XM0CSN1 (0x18000000) 24259701Sdim#define S3C64XX_PA_XM0CSN2 (0x20000000) 25259701Sdim#define S3C64XX_PA_XM0CSN3 (0x28000000) 26259701Sdim#define S3C64XX_PA_XM0CSN4 (0x30000000) 27259701Sdim#define S3C64XX_PA_XM0CSN5 (0x38000000) 28259701Sdim 29259701Sdim/* HSMMC units */ 30259701Sdim#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) 31259701Sdim#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) 32259701Sdim#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) 33259701Sdim#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) 34259701Sdim 35259701Sdim#define S3C_PA_UART (0x7F005000) 36259701Sdim#define S3C_PA_UART0 (S3C_PA_UART + 0x00) 37259701Sdim#define S3C_PA_UART1 (S3C_PA_UART + 0x400) 38259701Sdim#define S3C_PA_UART2 (S3C_PA_UART + 0x800) 39259701Sdim#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) 40259701Sdim#define S3C_UART_OFFSET (0x400) 41259701Sdim 42259701Sdim/* See notes on UART VA mapping in debug-macro.S */ 43259701Sdim#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) 44259701Sdim 45259701Sdim#define S3C_VA_UART0 S3C_VA_UARTx(0) 46259701Sdim#define S3C_VA_UART1 S3C_VA_UARTx(1) 47259701Sdim#define S3C_VA_UART2 S3C_VA_UARTx(2) 48259701Sdim#define S3C_VA_UART3 S3C_VA_UARTx(3) 49259701Sdim 50259701Sdim#define S3C64XX_PA_SROM (0x70000000) 51259701Sdim 52259701Sdim#define S3C64XX_PA_ONENAND0 (0x70100000) 53259701Sdim#define S3C64XX_PA_ONENAND0_BUF (0x20000000) 54259701Sdim#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) 55259701Sdim 56259701Sdim/* NAND and OneNAND1 controllers occupy the same register region 57259701Sdim (depending on SoC POP version) */ 58259701Sdim#define S3C64XX_PA_ONENAND1 (0x70200000) 59259701Sdim#define S3C64XX_PA_ONENAND1_BUF (0x28000000) 60259701Sdim#define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) 61259701Sdim 62259701Sdim#define S3C64XX_PA_NAND (0x70200000) 63259701Sdim#define S3C64XX_PA_FB (0x77100000) 64259701Sdim#define S3C64XX_PA_USB_HSOTG (0x7C000000) 65259701Sdim#define S3C64XX_PA_WATCHDOG (0x7E004000) 66259701Sdim#define S3C64XX_PA_RTC (0x7E005000) 67259701Sdim#define S3C64XX_PA_KEYPAD (0x7E00A000) 68259701Sdim#define S3C64XX_PA_ADC (0x7E00B000) 69259701Sdim#define S3C64XX_PA_SYSCON (0x7E00F000) 70259701Sdim#define S3C64XX_PA_AC97 (0x7F001000) 71259701Sdim#define S3C64XX_PA_IIS0 (0x7F002000) 72259701Sdim#define S3C64XX_PA_IIS1 (0x7F003000) 73259701Sdim#define S3C64XX_PA_TIMER (0x7F006000) 74259701Sdim#define S3C64XX_PA_IIC0 (0x7F004000) 75259701Sdim#define S3C64XX_PA_SPI0 (0x7F00B000) 76259701Sdim#define S3C64XX_PA_SPI1 (0x7F00C000) 77259701Sdim#define S3C64XX_PA_PCM0 (0x7F009000) 78259701Sdim#define S3C64XX_PA_PCM1 (0x7F00A000) 79259701Sdim#define S3C64XX_PA_IISV4 (0x7F00D000) 80259701Sdim#define S3C64XX_PA_IIC1 (0x7F00F000) 81259701Sdim 82259701Sdim#define S3C64XX_PA_GPIO (0x7F008000) 83259701Sdim#define S3C64XX_SZ_GPIO SZ_4K 84259701Sdim 85259701Sdim#define S3C64XX_PA_SDRAM (0x50000000) 86259701Sdim 87259701Sdim#define S3C64XX_PA_CFCON (0x70300000) 88259701Sdim 89259701Sdim#define S3C64XX_PA_VIC0 (0x71200000) 90259701Sdim#define S3C64XX_PA_VIC1 (0x71300000) 91259701Sdim 92259701Sdim#define S3C64XX_PA_MODEM (0x74108000) 93259701Sdim 94259701Sdim#define S3C64XX_PA_USBHOST (0x74300000) 95259701Sdim 96259701Sdim#define S3C64XX_PA_USB_HSPHY (0x7C100000) 97259701Sdim 98259701Sdim/* compatibility defines. */ 99259701Sdim#define S3C_PA_TIMER S3C64XX_PA_TIMER 100259701Sdim#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 101259701Sdim#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 102259701Sdim#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 103259701Sdim#define S3C_PA_IIC S3C64XX_PA_IIC0 104259701Sdim#define S3C_PA_IIC1 S3C64XX_PA_IIC1 105259701Sdim#define S3C_PA_NAND S3C64XX_PA_NAND 106259701Sdim#define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 107259701Sdim#define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF 108259701Sdim#define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF 109259701Sdim#define S3C_PA_FB S3C64XX_PA_FB 110259701Sdim#define S3C_PA_USBHOST S3C64XX_PA_USBHOST 111259701Sdim#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 112259701Sdim#define S3C_PA_RTC S3C64XX_PA_RTC 113259701Sdim#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 114259701Sdim#define S3C_PA_SPI0 S3C64XX_PA_SPI0 115259701Sdim#define S3C_PA_SPI1 S3C64XX_PA_SPI1 116259701Sdim 117259701Sdim#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 118259701Sdim#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 119259701Sdim#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD 120259701Sdim#define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER 121259701Sdim 122259701Sdim#endif /* __ASM_ARCH_6400_MAP_H */ 123259701Sdim