1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-orion5x/pci.c
4 *
5 * PCI and PCIe functions for Marvell Orion System On Chip
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/mbus.h>
14#include <video/vga.h>
15#include <asm/irq.h>
16#include <asm/mach/pci.h>
17#include <plat/pcie.h>
18#include <plat/addr-map.h>
19#include "common.h"
20#include "orion5x.h"
21
22/*****************************************************************************
23 * Orion has one PCIe controller and one PCI controller.
24 *
25 * Note1: The local PCIe bus number is '0'. The local PCI bus number
26 * follows the scanned PCIe bridged busses, if any.
27 *
28 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
29 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
30 * device bus, Orion registers, etc. However this code only enable the
31 * access to DDR banks.
32 ****************************************************************************/
33
34
35/*****************************************************************************
36 * PCIe controller
37 ****************************************************************************/
38#define PCIE_BASE	(ORION5X_PCIE_VIRT_BASE)
39
40void __init orion5x_pcie_id(u32 *dev, u32 *rev)
41{
42	*dev = orion_pcie_dev_id(PCIE_BASE);
43	*rev = orion_pcie_rev(PCIE_BASE);
44}
45
46static int pcie_valid_config(int bus, int dev)
47{
48	/*
49	 * Don't go out when trying to access --
50	 * 1. nonexisting device on local bus
51	 * 2. where there's no device connected (no link)
52	 */
53	if (bus == 0 && dev == 0)
54		return 1;
55
56	if (!orion_pcie_link_up(PCIE_BASE))
57		return 0;
58
59	if (bus == 0 && dev != 1)
60		return 0;
61
62	return 1;
63}
64
65
66/*
67 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
68 * and then reading the PCIE_CONF_DATA register. Need to make sure these
69 * transactions are atomic.
70 */
71static DEFINE_SPINLOCK(orion5x_pcie_lock);
72
73static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
74			int size, u32 *val)
75{
76	unsigned long flags;
77	int ret;
78
79	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
80		*val = 0xffffffff;
81		return PCIBIOS_DEVICE_NOT_FOUND;
82	}
83
84	spin_lock_irqsave(&orion5x_pcie_lock, flags);
85	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
86	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
87
88	return ret;
89}
90
91static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
92			   int where, int size, u32 *val)
93{
94	int ret;
95
96	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
97		*val = 0xffffffff;
98		return PCIBIOS_DEVICE_NOT_FOUND;
99	}
100
101	/*
102	 * We only support access to the non-extended configuration
103	 * space when using the WA access method (or we would have to
104	 * sacrifice 256M of CPU virtual address space.)
105	 */
106	if (where >= 0x100) {
107		*val = 0xffffffff;
108		return PCIBIOS_DEVICE_NOT_FOUND;
109	}
110
111	ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
112				    bus, devfn, where, size, val);
113
114	return ret;
115}
116
117static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
118			int where, int size, u32 val)
119{
120	unsigned long flags;
121	int ret;
122
123	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
124		return PCIBIOS_DEVICE_NOT_FOUND;
125
126	spin_lock_irqsave(&orion5x_pcie_lock, flags);
127	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
128	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
129
130	return ret;
131}
132
133static struct pci_ops pcie_ops = {
134	.read = pcie_rd_conf,
135	.write = pcie_wr_conf,
136};
137
138
139static int __init pcie_setup(struct pci_sys_data *sys)
140{
141	struct resource *res;
142	struct resource realio;
143	int dev;
144
145	/*
146	 * Generic PCIe unit setup.
147	 */
148	orion_pcie_setup(PCIE_BASE);
149
150	/*
151	 * Check whether to apply Orion-1/Orion-NAS PCIe config
152	 * read transaction workaround.
153	 */
154	dev = orion_pcie_dev_id(PCIE_BASE);
155	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
156		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
157				   "read transaction workaround\n");
158		mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
159					    ORION_MBUS_PCIE_WA_ATTR,
160					    ORION5X_PCIE_WA_PHYS_BASE,
161					    ORION5X_PCIE_WA_SIZE);
162		pcie_ops.read = pcie_rd_conf_wa;
163	}
164
165	realio.start = sys->busnr * SZ_64K;
166	realio.end = realio.start + SZ_64K - 1;
167	pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
168
169	/*
170	 * Request resources.
171	 */
172	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
173	if (!res)
174		panic("pcie_setup unable to alloc resources");
175
176	/*
177	 * IORESOURCE_MEM
178	 */
179	res->name = "PCIe Memory Space";
180	res->flags = IORESOURCE_MEM;
181	res->start = ORION5X_PCIE_MEM_PHYS_BASE;
182	res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
183	if (request_resource(&iomem_resource, res))
184		panic("Request PCIe Memory resource failed\n");
185	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
186
187	return 1;
188}
189
190/*****************************************************************************
191 * PCI controller
192 ****************************************************************************/
193#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE + (x))
194#define PCI_MODE		ORION5X_PCI_REG(0xd00)
195#define PCI_CMD			ORION5X_PCI_REG(0xc00)
196#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
197#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
198#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)
199
200/*
201 * PCI_MODE bits
202 */
203#define PCI_MODE_64BIT			(1 << 2)
204#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))
205
206/*
207 * PCI_CMD bits
208 */
209#define PCI_CMD_HOST_REORDER		(1 << 29)
210
211/*
212 * PCI_P2P_CONF bits
213 */
214#define PCI_P2P_BUS_OFFS		16
215#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
216#define PCI_P2P_DEV_OFFS		24
217#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)
218
219/*
220 * PCI_CONF_ADDR bits
221 */
222#define PCI_CONF_REG(reg)		((reg) & 0xfc)
223#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
224#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
225#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
226#define PCI_CONF_ADDR_EN		(1 << 31)
227
228/*
229 * Internal configuration space
230 */
231#define PCI_CONF_FUNC_STAT_CMD		0
232#define PCI_CONF_REG_STAT_CMD		4
233#define PCIX_STAT			0x64
234#define PCIX_STAT_BUS_OFFS		8
235#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)
236
237/*
238 * PCI Address Decode Windows registers
239 */
240#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
241				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
242				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
243				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
244#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
245				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
246				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
247				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
248#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
249#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)
250
251/*
252 * PCI configuration helpers for BAR settings
253 */
254#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
255#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
256#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
257
258/*
259 * PCI config cycles are done by programming the PCI_CONF_ADDR register
260 * and then reading the PCI_CONF_DATA register. Need to make sure these
261 * transactions are atomic.
262 */
263static DEFINE_SPINLOCK(orion5x_pci_lock);
264
265static int orion5x_pci_cardbus_mode;
266
267static int orion5x_pci_local_bus_nr(void)
268{
269	u32 conf = readl(PCI_P2P_CONF);
270	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
271}
272
273static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
274					u32 where, u32 size, u32 *val)
275{
276	unsigned long flags;
277	spin_lock_irqsave(&orion5x_pci_lock, flags);
278
279	writel(PCI_CONF_BUS(bus) |
280		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
281		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
282
283	*val = readl(PCI_CONF_DATA);
284
285	if (size == 1)
286		*val = (*val >> (8*(where & 0x3))) & 0xff;
287	else if (size == 2)
288		*val = (*val >> (8*(where & 0x3))) & 0xffff;
289
290	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
291
292	return PCIBIOS_SUCCESSFUL;
293}
294
295static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
296					u32 where, u32 size, u32 val)
297{
298	unsigned long flags;
299	int ret = PCIBIOS_SUCCESSFUL;
300
301	spin_lock_irqsave(&orion5x_pci_lock, flags);
302
303	writel(PCI_CONF_BUS(bus) |
304		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
305		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
306
307	if (size == 4) {
308		__raw_writel(val, PCI_CONF_DATA);
309	} else if (size == 2) {
310		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
311	} else if (size == 1) {
312		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
313	} else {
314		ret = PCIBIOS_BAD_REGISTER_NUMBER;
315	}
316
317	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
318
319	return ret;
320}
321
322static int orion5x_pci_valid_config(int bus, u32 devfn)
323{
324	if (bus == orion5x_pci_local_bus_nr()) {
325		/*
326		 * Don't go out for local device
327		 */
328		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
329			return 0;
330
331		/*
332		 * When the PCI signals are directly connected to a
333		 * Cardbus slot, ignore all but device IDs 0 and 1.
334		 */
335		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
336			return 0;
337	}
338
339	return 1;
340}
341
342static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
343				int where, int size, u32 *val)
344{
345	if (!orion5x_pci_valid_config(bus->number, devfn)) {
346		*val = 0xffffffff;
347		return PCIBIOS_DEVICE_NOT_FOUND;
348	}
349
350	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
351					PCI_FUNC(devfn), where, size, val);
352}
353
354static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
355				int where, int size, u32 val)
356{
357	if (!orion5x_pci_valid_config(bus->number, devfn))
358		return PCIBIOS_DEVICE_NOT_FOUND;
359
360	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
361					PCI_FUNC(devfn), where, size, val);
362}
363
364static struct pci_ops pci_ops = {
365	.read = orion5x_pci_rd_conf,
366	.write = orion5x_pci_wr_conf,
367};
368
369static void __init orion5x_pci_set_bus_nr(int nr)
370{
371	u32 p2p = readl(PCI_P2P_CONF);
372
373	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
374		/*
375		 * PCI-X mode
376		 */
377		u32 pcix_status, bus, dev;
378		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
379		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
380		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
381		pcix_status &= ~PCIX_STAT_BUS_MASK;
382		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
383		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
384	} else {
385		/*
386		 * PCI Conventional mode
387		 */
388		p2p &= ~PCI_P2P_BUS_MASK;
389		p2p |= (nr << PCI_P2P_BUS_OFFS);
390		writel(p2p, PCI_P2P_CONF);
391	}
392}
393
394static void __init orion5x_pci_master_slave_enable(void)
395{
396	int bus_nr, func, reg;
397	u32 val;
398
399	bus_nr = orion5x_pci_local_bus_nr();
400	func = PCI_CONF_FUNC_STAT_CMD;
401	reg = PCI_CONF_REG_STAT_CMD;
402	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
403	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
404	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
405}
406
407static void __init orion5x_setup_pci_wins(void)
408{
409	const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
410	u32 win_enable;
411	int bus;
412	int i;
413
414	/*
415	 * First, disable windows.
416	 */
417	win_enable = 0xffffffff;
418	writel(win_enable, PCI_BAR_ENABLE);
419
420	/*
421	 * Setup windows for DDR banks.
422	 */
423	bus = orion5x_pci_local_bus_nr();
424
425	for (i = 0; i < dram->num_cs; i++) {
426		const struct mbus_dram_window *cs = dram->cs + i;
427		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
428		u32 reg;
429		u32 val;
430
431		/*
432		 * Write DRAM bank base address register.
433		 */
434		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
435		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
436		val = (cs->base & 0xfffff000) | (val & 0xfff);
437		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
438
439		/*
440		 * Write DRAM bank size register.
441		 */
442		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
443		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
444		writel((cs->size - 1) & 0xfffff000,
445			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
446		writel(cs->base & 0xfffff000,
447			PCI_BAR_REMAP_DDR_CS(cs->cs_index));
448
449		/*
450		 * Enable decode window for this chip select.
451		 */
452		win_enable &= ~(1 << cs->cs_index);
453	}
454
455	/*
456	 * Re-enable decode windows.
457	 */
458	writel(win_enable, PCI_BAR_ENABLE);
459
460	/*
461	 * Disable automatic update of address remapping when writing to BARs.
462	 */
463	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
464}
465
466static int __init pci_setup(struct pci_sys_data *sys)
467{
468	struct resource *res;
469	struct resource realio;
470
471	/*
472	 * Point PCI unit MBUS decode windows to DRAM space.
473	 */
474	orion5x_setup_pci_wins();
475
476	/*
477	 * Master + Slave enable
478	 */
479	orion5x_pci_master_slave_enable();
480
481	/*
482	 * Force ordering
483	 */
484	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
485
486	realio.start = sys->busnr * SZ_64K;
487	realio.end = realio.start + SZ_64K - 1;
488	pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
489
490	/*
491	 * Request resources
492	 */
493	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
494	if (!res)
495		panic("pci_setup unable to alloc resources");
496
497	/*
498	 * IORESOURCE_MEM
499	 */
500	res->name = "PCI Memory Space";
501	res->flags = IORESOURCE_MEM;
502	res->start = ORION5X_PCI_MEM_PHYS_BASE;
503	res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
504	if (request_resource(&iomem_resource, res))
505		panic("Request PCI Memory resource failed\n");
506	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
507
508	return 1;
509}
510
511
512/*****************************************************************************
513 * General PCIe + PCI
514 ****************************************************************************/
515
516/*
517 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
518 * is operating as a root complex this needs to be switched to
519 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
520 * the device. Decoding setup is handled by the orion code.
521 */
522static void rc_pci_fixup(struct pci_dev *dev)
523{
524	if (dev->bus->parent == NULL && dev->devfn == 0) {
525		struct resource *r;
526
527		dev->class &= 0xff;
528		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
529		pci_dev_for_each_resource(dev, r) {
530			r->start	= 0;
531			r->end		= 0;
532			r->flags	= 0;
533		}
534	}
535}
536DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
537
538static int orion5x_pci_disabled __initdata;
539
540void __init orion5x_pci_disable(void)
541{
542	orion5x_pci_disabled = 1;
543}
544
545void __init orion5x_pci_set_cardbus_mode(void)
546{
547	orion5x_pci_cardbus_mode = 1;
548}
549
550int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
551{
552	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
553
554	if (nr == 0) {
555		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
556		return pcie_setup(sys);
557	}
558
559	if (nr == 1 && !orion5x_pci_disabled) {
560		orion5x_pci_set_bus_nr(sys->busnr);
561		return pci_setup(sys);
562	}
563
564	return 0;
565}
566
567int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
568{
569	struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
570
571	list_splice_init(&sys->resources, &bridge->windows);
572	bridge->dev.parent = NULL;
573	bridge->sysdata = sys;
574	bridge->busnr = sys->busnr;
575
576	if (nr == 0) {
577		bridge->ops = &pcie_ops;
578		return pci_scan_root_bus_bridge(bridge);
579	}
580
581	if (nr == 1 && !orion5x_pci_disabled) {
582		bridge->ops = &pci_ops;
583		return pci_scan_root_bus_bridge(bridge);
584	}
585
586	BUG();
587	return -ENODEV;
588}
589
590int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
591{
592	int bus = dev->bus->number;
593
594	/*
595	 * PCIe endpoint?
596	 */
597	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
598		return IRQ_ORION5X_PCIE0_INT;
599
600	return -1;
601}
602