1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions 4 * 5 * Copyright (C) 2005-2009 Texas Instruments, Inc. 6 * Copyright (C) 2004-2009 Nokia Corporation 7 * 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * 10 * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 11 * These configurations are characterized by voltage and speed for clocks. 12 * The device is only validated for certain combinations. One way to express 13 * these combinations is via the 'ratio's' which the clocks operate with 14 * respect to each other. These ratio sets are for a given voltage/DPLL 15 * setting. All configurations can be described by a DPLL setting and a ratio 16 * There are 3 ratio sets for the 2430 and X ratio sets for 2420. 17 * 18 * 2430 differs from 2420 in that there are no more phase synchronizers used. 19 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 20 * 2430 (iva2.1, NOdsp, mdm) 21 * 22 * XXX Missing voltage data. 23 * 24 * THe format described in this file is deprecated. Once a reasonable 25 * OPP API exists, the data in this file should be converted to use it. 26 * 27 * This is technically part of the OMAP2xxx clock code. 28 */ 29 30#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 31#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 32 33/** 34 * struct prcm_config - define clock rates on a per-OPP basis (24xx) 35 * 36 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 39 * 40 * This is deprecated. As soon as we have a decent OPP API, we should 41 * move all this stuff to it. 42 */ 43struct prcm_config { 44 unsigned long xtal_speed; /* crystal rate */ 45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ 46 unsigned long mpu_speed; /* speed of MPU */ 47 unsigned long cm_clksel_mpu; /* mpu divider */ 48 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ 49 unsigned long cm_clksel_gfx; /* gfx dividers */ 50 unsigned long cm_clksel1_core; /* major subsystem dividers */ 51 unsigned long cm_clksel1_pll; /* m,n */ 52 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 53 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 54 unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 55 unsigned short flags; 56}; 57 58 59/* Core fields for cm_clksel, not ratio governed */ 60#define RX_CLKSEL_DSS1 (0x10 << 8) 61#define RX_CLKSEL_DSS2 (0x0 << 13) 62#define RX_CLKSEL_SSI (0x5 << 20) 63 64/*------------------------------------------------------------------------- 65 * Voltage/DPLL ratios 66 *-------------------------------------------------------------------------*/ 67 68/* 2430 Ratio's, 2430-Ratio Config 1 */ 69#define R1_CLKSEL_L3 (4 << 0) 70#define R1_CLKSEL_L4 (2 << 5) 71#define R1_CLKSEL_USB (4 << 25) 72#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ 73 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 74 R1_CLKSEL_L4 | R1_CLKSEL_L3) 75#define R1_CLKSEL_MPU (2 << 0) 76#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU 77#define R1_CLKSEL_DSP (2 << 0) 78#define R1_CLKSEL_DSP_IF (2 << 5) 79#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) 80#define R1_CLKSEL_GFX (2 << 0) 81#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX 82#define R1_CLKSEL_MDM (4 << 0) 83#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM 84 85/* 2430-Ratio Config 2 */ 86#define R2_CLKSEL_L3 (6 << 0) 87#define R2_CLKSEL_L4 (2 << 5) 88#define R2_CLKSEL_USB (2 << 25) 89#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ 90 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 91 R2_CLKSEL_L4 | R2_CLKSEL_L3) 92#define R2_CLKSEL_MPU (2 << 0) 93#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU 94#define R2_CLKSEL_DSP (2 << 0) 95#define R2_CLKSEL_DSP_IF (3 << 5) 96#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) 97#define R2_CLKSEL_GFX (2 << 0) 98#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX 99#define R2_CLKSEL_MDM (6 << 0) 100#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM 101 102/* 2430-Ratio Bootm (BYPASS) */ 103#define RB_CLKSEL_L3 (1 << 0) 104#define RB_CLKSEL_L4 (1 << 5) 105#define RB_CLKSEL_USB (1 << 25) 106#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ 107 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 108 RB_CLKSEL_L4 | RB_CLKSEL_L3) 109#define RB_CLKSEL_MPU (1 << 0) 110#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU 111#define RB_CLKSEL_DSP (1 << 0) 112#define RB_CLKSEL_DSP_IF (1 << 5) 113#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) 114#define RB_CLKSEL_GFX (1 << 0) 115#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX 116#define RB_CLKSEL_MDM (1 << 0) 117#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM 118 119/* 2420 Ratio Equivalents */ 120#define RXX_CLKSEL_VLYNQ (0x12 << 15) 121#define RXX_CLKSEL_SSI (0x8 << 20) 122 123/* 2420-PRCM III 532MHz core */ 124#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ 125#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ 126#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ 127#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 128 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 129 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ 130 RIII_CLKSEL_L3) 131#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ 132#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU 133#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ 134#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ 135#define RIII_SYNC_DSP (1 << 7) /* Enable sync */ 136#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ 137#define RIII_SYNC_IVA (1 << 13) /* Enable sync */ 138#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ 139 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ 140 RIII_CLKSEL_DSP) 141#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ 142#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX 143 144/* 2420-PRCM II 600MHz core */ 145#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ 146#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ 147#define RII_CLKSEL_USB (2 << 25) /* 50MHz */ 148#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 149 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 150 RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ 151 RII_CLKSEL_L3) 152#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ 153#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU 154#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ 155#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ 156#define RII_SYNC_DSP (0 << 7) /* Bypass sync */ 157#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ 158#define RII_SYNC_IVA (0 << 13) /* Bypass sync */ 159#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ 160 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ 161 RII_CLKSEL_DSP) 162#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ 163#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX 164 165/* 2420-PRCM I 660MHz core */ 166#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ 167#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ 168#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ 169#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ 170 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 171 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 172 RI_CLKSEL_L4 | RI_CLKSEL_L3) 173#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ 174#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU 175#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ 176#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ 177#define RI_SYNC_DSP (1 << 7) /* Activate sync */ 178#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ 179#define RI_SYNC_IVA (0 << 13) /* Bypass sync */ 180#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ 181 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ 182 RI_CLKSEL_DSP) 183#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ 184#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX 185 186/* 2420-PRCM VII (boot) */ 187#define RVII_CLKSEL_L3 (1 << 0) 188#define RVII_CLKSEL_L4 (1 << 5) 189#define RVII_CLKSEL_DSS1 (1 << 8) 190#define RVII_CLKSEL_DSS2 (0 << 13) 191#define RVII_CLKSEL_VLYNQ (1 << 15) 192#define RVII_CLKSEL_SSI (1 << 20) 193#define RVII_CLKSEL_USB (1 << 25) 194 195#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ 196 RVII_CLKSEL_VLYNQ | \ 197 RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ 198 RVII_CLKSEL_L4 | RVII_CLKSEL_L3) 199 200#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ 201#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU 202 203#define RVII_CLKSEL_DSP (1 << 0) 204#define RVII_CLKSEL_DSP_IF (1 << 5) 205#define RVII_SYNC_DSP (0 << 7) 206#define RVII_CLKSEL_IVA (1 << 8) 207#define RVII_SYNC_IVA (0 << 13) 208#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ 209 RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ 210 RVII_CLKSEL_DSP) 211 212#define RVII_CLKSEL_GFX (1 << 0) 213#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX 214 215/*------------------------------------------------------------------------- 216 * 2430 Target modes: Along with each configuration the CPU has several 217 * modes which goes along with them. Modes mainly are the addition of 218 * describe DPLL combinations to go along with a ratio. 219 *-------------------------------------------------------------------------*/ 220 221/* Hardware governed */ 222#define MX_48M_SRC (0 << 3) 223#define MX_54M_SRC (0 << 5) 224#define MX_APLLS_CLIKIN_12 (3 << 23) 225#define MX_APLLS_CLIKIN_13 (2 << 23) 226#define MX_APLLS_CLIKIN_19_2 (0 << 23) 227 228/* 229 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed 230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz 231 */ 232#define M5A_DPLL_MULT_12 (133 << 12) 233#define M5A_DPLL_DIV_12 (5 << 8) 234#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 235 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ 236 MX_APLLS_CLIKIN_12) 237#define M5A_DPLL_MULT_13 (61 << 12) 238#define M5A_DPLL_DIV_13 (2 << 8) 239#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 240 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ 241 MX_APLLS_CLIKIN_13) 242#define M5A_DPLL_MULT_19 (55 << 12) 243#define M5A_DPLL_DIV_19 (3 << 8) 244#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 245 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ 246 MX_APLLS_CLIKIN_19_2) 247/* #5b (ratio1) target DPLL = 200*2 = 400MHz */ 248#define M5B_DPLL_MULT_12 (50 << 12) 249#define M5B_DPLL_DIV_12 (2 << 8) 250#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 251 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ 252 MX_APLLS_CLIKIN_12) 253#define M5B_DPLL_MULT_13 (200 << 12) 254#define M5B_DPLL_DIV_13 (12 << 8) 255 256#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 257 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ 258 MX_APLLS_CLIKIN_13) 259#define M5B_DPLL_MULT_19 (125 << 12) 260#define M5B_DPLL_DIV_19 (31 << 8) 261#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 262 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ 263 MX_APLLS_CLIKIN_19_2) 264/* 265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 266 */ 267#define M4_DPLL_MULT_12 (133 << 12) 268#define M4_DPLL_DIV_12 (3 << 8) 269#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 270 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ 271 MX_APLLS_CLIKIN_12) 272 273#define M4_DPLL_MULT_13 (399 << 12) 274#define M4_DPLL_DIV_13 (12 << 8) 275#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 276 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ 277 MX_APLLS_CLIKIN_13) 278 279#define M4_DPLL_MULT_19 (145 << 12) 280#define M4_DPLL_DIV_19 (6 << 8) 281#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 282 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ 283 MX_APLLS_CLIKIN_19_2) 284 285/* 286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz 287 */ 288#define M3_DPLL_MULT_12 (55 << 12) 289#define M3_DPLL_DIV_12 (1 << 8) 290#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 291 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ 292 MX_APLLS_CLIKIN_12) 293#define M3_DPLL_MULT_13 (76 << 12) 294#define M3_DPLL_DIV_13 (2 << 8) 295#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 296 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ 297 MX_APLLS_CLIKIN_13) 298#define M3_DPLL_MULT_19 (17 << 12) 299#define M3_DPLL_DIV_19 (0 << 8) 300#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 301 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ 302 MX_APLLS_CLIKIN_19_2) 303 304/* 305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz 306 */ 307#define M2_DPLL_MULT_12 (55 << 12) 308#define M2_DPLL_DIV_12 (1 << 8) 309#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 310 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ 311 MX_APLLS_CLIKIN_12) 312 313/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, 314 * relock time issue */ 315/* Core frequency changed from 330/165 to 329/164 MHz*/ 316#define M2_DPLL_MULT_13 (76 << 12) 317#define M2_DPLL_DIV_13 (2 << 8) 318#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 319 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ 320 MX_APLLS_CLIKIN_13) 321 322#define M2_DPLL_MULT_19 (17 << 12) 323#define M2_DPLL_DIV_19 (0 << 8) 324#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 325 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ 326 MX_APLLS_CLIKIN_19_2) 327 328/* boot (boot) */ 329#define MB_DPLL_MULT (1 << 12) 330#define MB_DPLL_DIV (0 << 8) 331#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 332 MB_DPLL_DIV | MB_DPLL_MULT | \ 333 MX_APLLS_CLIKIN_12) 334 335#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 336 MB_DPLL_DIV | MB_DPLL_MULT | \ 337 MX_APLLS_CLIKIN_13) 338 339#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 340 MB_DPLL_DIV | MB_DPLL_MULT | \ 341 MX_APLLS_CLIKIN_19) 342 343/* 344 * 2430 - chassis (sedna) 345 * 165 (ratio1) same as above #2 346 * 150 (ratio1) 347 * 133 (ratio2) same as above #4 348 * 110 (ratio2) same as above #3 349 * 104 (ratio2) 350 * boot (boot) 351 */ 352 353/* PRCM I target DPLL = 2*330MHz = 660MHz */ 354#define MI_DPLL_MULT_12 (55 << 12) 355#define MI_DPLL_DIV_12 (1 << 8) 356#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 357 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ 358 MX_APLLS_CLIKIN_12) 359 360/* 361 * 2420 Equivalent - mode registers 362 * PRCM II , target DPLL = 2*300MHz = 600MHz 363 */ 364#define MII_DPLL_MULT_12 (50 << 12) 365#define MII_DPLL_DIV_12 (1 << 8) 366#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 367 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ 368 MX_APLLS_CLIKIN_12) 369#define MII_DPLL_MULT_13 (300 << 12) 370#define MII_DPLL_DIV_13 (12 << 8) 371#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 372 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ 373 MX_APLLS_CLIKIN_13) 374 375/* PRCM III target DPLL = 2*266 = 532MHz*/ 376#define MIII_DPLL_MULT_12 (133 << 12) 377#define MIII_DPLL_DIV_12 (5 << 8) 378#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 379 MIII_DPLL_DIV_12 | \ 380 MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) 381#define MIII_DPLL_MULT_13 (266 << 12) 382#define MIII_DPLL_DIV_13 (12 << 8) 383#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 384 MIII_DPLL_DIV_13 | \ 385 MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) 386 387/* PRCM VII (boot bypass) */ 388#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL 389#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL 390 391/* High and low operation value */ 392#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) 393#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) 394 395/* MPU speed defines */ 396#define S12M 12000000 397#define S13M 13000000 398#define S19M 19200000 399#define S26M 26000000 400#define S100M 100000000 401#define S133M 133000000 402#define S150M 150000000 403#define S164M 164000000 404#define S165M 165000000 405#define S199M 199000000 406#define S200M 200000000 407#define S266M 266000000 408#define S300M 300000000 409#define S329M 329000000 410#define S330M 330000000 411#define S399M 399000000 412#define S400M 400000000 413#define S532M 532000000 414#define S600M 600000000 415#define S658M 658000000 416#define S660M 660000000 417#define S798M 798000000 418 419 420extern const struct prcm_config omap2420_rate_table[]; 421 422#ifdef CONFIG_SOC_OMAP2430 423extern const struct prcm_config omap2430_rate_table[]; 424#else 425#define omap2430_rate_table NULL 426#endif 427extern const struct prcm_config *rate_table; 428extern const struct prcm_config *curr_prcm_set; 429 430#endif 431