1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * OMAP2/3 System Control Module register access 4 * 5 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 6 * Copyright (C) 2007 Nokia Corporation 7 * 8 * Written by Paul Walmsley 9 */ 10#undef DEBUG 11 12#include <linux/kernel.h> 13#include <linux/io.h> 14#include <linux/of_address.h> 15#include <linux/regmap.h> 16#include <linux/mfd/syscon.h> 17#include <linux/cpu_pm.h> 18 19#include "soc.h" 20#include "iomap.h" 21#include "common.h" 22#include "cm-regbits-34xx.h" 23#include "prm-regbits-34xx.h" 24#include "prm3xxx.h" 25#include "cm3xxx.h" 26#include "sdrc.h" 27#include "pm.h" 28#include "control.h" 29#include "clock.h" 30 31/* Used by omap3_ctrl_save_padconf() */ 32#define START_PADCONF_SAVE 0x2 33#define PADCONF_SAVE_DONE 0x1 34 35static void __iomem *omap2_ctrl_base; 36static s16 omap2_ctrl_offset; 37 38#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 39struct omap3_scratchpad { 40 u32 boot_config_ptr; 41 u32 public_restore_ptr; 42 u32 secure_ram_restore_ptr; 43 u32 sdrc_module_semaphore; 44 u32 prcm_block_offset; 45 u32 sdrc_block_offset; 46}; 47 48struct omap3_scratchpad_prcm_block { 49 u32 prm_contents[2]; 50 u32 cm_contents[11]; 51 u32 prcm_block_size; 52}; 53 54struct omap3_scratchpad_sdrc_block { 55 u16 sysconfig; 56 u16 cs_cfg; 57 u16 sharing; 58 u16 err_type; 59 u32 dll_a_ctrl; 60 u32 dll_b_ctrl; 61 u32 power; 62 u32 cs_0; 63 u32 mcfg_0; 64 u16 mr_0; 65 u16 emr_1_0; 66 u16 emr_2_0; 67 u16 emr_3_0; 68 u32 actim_ctrla_0; 69 u32 actim_ctrlb_0; 70 u32 rfr_ctrl_0; 71 u32 cs_1; 72 u32 mcfg_1; 73 u16 mr_1; 74 u16 emr_1_1; 75 u16 emr_2_1; 76 u16 emr_3_1; 77 u32 actim_ctrla_1; 78 u32 actim_ctrlb_1; 79 u32 rfr_ctrl_1; 80 u16 dcdl_1_ctrl; 81 u16 dcdl_2_ctrl; 82 u32 flags; 83 u32 block_size; 84}; 85 86void *omap3_secure_ram_storage; 87 88/* 89 * This is used to store ARM registers in SDRAM before attempting 90 * an MPU OFF. The save and restore happens from the SRAM sleep code. 91 * The address is stored in scratchpad, so that it can be used 92 * during the restore path. 93 */ 94u32 omap3_arm_context[128]; 95 96struct omap3_control_regs { 97 u32 sysconfig; 98 u32 devconf0; 99 u32 mem_dftrw0; 100 u32 mem_dftrw1; 101 u32 msuspendmux_0; 102 u32 msuspendmux_1; 103 u32 msuspendmux_2; 104 u32 msuspendmux_3; 105 u32 msuspendmux_4; 106 u32 msuspendmux_5; 107 u32 sec_ctrl; 108 u32 devconf1; 109 u32 csirxfe; 110 u32 iva2_bootaddr; 111 u32 iva2_bootmod; 112 u32 wkup_ctrl; 113 u32 debobs_0; 114 u32 debobs_1; 115 u32 debobs_2; 116 u32 debobs_3; 117 u32 debobs_4; 118 u32 debobs_5; 119 u32 debobs_6; 120 u32 debobs_7; 121 u32 debobs_8; 122 u32 prog_io0; 123 u32 prog_io1; 124 u32 dss_dpll_spreading; 125 u32 core_dpll_spreading; 126 u32 per_dpll_spreading; 127 u32 usbhost_dpll_spreading; 128 u32 pbias_lite; 129 u32 temp_sensor; 130 u32 sramldo4; 131 u32 sramldo5; 132 u32 csi; 133 u32 padconf_sys_nirq; 134}; 135 136static struct omap3_control_regs control_context; 137#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 138 139u8 omap_ctrl_readb(u16 offset) 140{ 141 u32 val; 142 u8 byte_offset = offset & 0x3; 143 144 val = omap_ctrl_readl(offset); 145 146 return (val >> (byte_offset * 8)) & 0xff; 147} 148 149u16 omap_ctrl_readw(u16 offset) 150{ 151 u32 val; 152 u16 byte_offset = offset & 0x2; 153 154 val = omap_ctrl_readl(offset); 155 156 return (val >> (byte_offset * 8)) & 0xffff; 157} 158 159u32 omap_ctrl_readl(u16 offset) 160{ 161 offset &= 0xfffc; 162 163 return readl_relaxed(omap2_ctrl_base + offset); 164} 165 166void omap_ctrl_writeb(u8 val, u16 offset) 167{ 168 u32 tmp; 169 u8 byte_offset = offset & 0x3; 170 171 tmp = omap_ctrl_readl(offset); 172 173 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); 174 tmp |= val << (byte_offset * 8); 175 176 omap_ctrl_writel(tmp, offset); 177} 178 179void omap_ctrl_writew(u16 val, u16 offset) 180{ 181 u32 tmp; 182 u8 byte_offset = offset & 0x2; 183 184 tmp = omap_ctrl_readl(offset); 185 186 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); 187 tmp |= val << (byte_offset * 8); 188 189 omap_ctrl_writel(tmp, offset); 190} 191 192void omap_ctrl_writel(u32 val, u16 offset) 193{ 194 offset &= 0xfffc; 195 writel_relaxed(val, omap2_ctrl_base + offset); 196} 197 198#ifdef CONFIG_ARCH_OMAP3 199 200/** 201 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 202 * @bootmode: 8-bit value to pass to some boot code 203 * 204 * Set the bootmode in the scratchpad RAM. This is used after the 205 * system restarts. Not sure what actually uses this - it may be the 206 * bootloader, rather than the boot ROM - contrary to the preserved 207 * comment below. No return value. 208 */ 209void omap3_ctrl_write_boot_mode(u8 bootmode) 210{ 211 u32 l; 212 213 l = ('B' << 24) | ('M' << 16) | bootmode; 214 215 /* 216 * Reserve the first word in scratchpad for communicating 217 * with the boot ROM. A pointer to a data structure 218 * describing the boot process can be stored there, 219 * cf. OMAP34xx TRM, Initialization / Software Booting 220 * Configuration. 221 * 222 * XXX This should use some omap_ctrl_writel()-type function 223 */ 224 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 225} 226 227#endif 228 229#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 230/* Populate the scratchpad structure with restore structure */ 231void omap3_save_scratchpad_contents(void) 232{ 233 void __iomem *scratchpad_address; 234 u32 arm_context_addr; 235 struct omap3_scratchpad scratchpad_contents; 236 struct omap3_scratchpad_prcm_block prcm_block_contents; 237 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 238 239 /* 240 * Populate the Scratchpad contents 241 * 242 * The "get_*restore_pointer" functions are used to provide a 243 * physical restore address where the ROM code jumps while waking 244 * up from MPU OFF/OSWR state. 245 * The restore pointer is stored into the scratchpad. 246 */ 247 scratchpad_contents.boot_config_ptr = 0x0; 248 if (cpu_is_omap3630()) 249 scratchpad_contents.public_restore_ptr = 250 __pa_symbol(omap3_restore_3630); 251 else if (omap_rev() != OMAP3430_REV_ES3_0 && 252 omap_rev() != OMAP3430_REV_ES3_1 && 253 omap_rev() != OMAP3430_REV_ES3_1_2) 254 scratchpad_contents.public_restore_ptr = 255 __pa_symbol(omap3_restore); 256 else 257 scratchpad_contents.public_restore_ptr = 258 __pa_symbol(omap3_restore_es3); 259 260 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 261 scratchpad_contents.secure_ram_restore_ptr = 0x0; 262 else 263 scratchpad_contents.secure_ram_restore_ptr = 264 (u32) __pa(omap3_secure_ram_storage); 265 scratchpad_contents.sdrc_module_semaphore = 0x0; 266 scratchpad_contents.prcm_block_offset = 0x2C; 267 scratchpad_contents.sdrc_block_offset = 0x64; 268 269 /* Populate the PRCM block contents */ 270 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 271 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 272 273 prcm_block_contents.prcm_block_size = 0x0; 274 275 /* Populate the SDRC block contents */ 276 sdrc_block_contents.sysconfig = 277 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 278 sdrc_block_contents.cs_cfg = 279 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 280 sdrc_block_contents.sharing = 281 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 282 sdrc_block_contents.err_type = 283 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 284 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 285 sdrc_block_contents.dll_b_ctrl = 0x0; 286 /* 287 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 288 * be programed to issue automatic self refresh on timeout 289 * of AUTO_CNT = 1 prior to any transition to OFF mode. 290 */ 291 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 292 && (omap_rev() >= OMAP3430_REV_ES3_0)) 293 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 294 ~(SDRC_POWER_AUTOCOUNT_MASK| 295 SDRC_POWER_CLKCTRL_MASK)) | 296 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 297 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 298 else 299 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 300 301 sdrc_block_contents.cs_0 = 0x0; 302 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 303 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 304 sdrc_block_contents.emr_1_0 = 0x0; 305 sdrc_block_contents.emr_2_0 = 0x0; 306 sdrc_block_contents.emr_3_0 = 0x0; 307 sdrc_block_contents.actim_ctrla_0 = 308 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 309 sdrc_block_contents.actim_ctrlb_0 = 310 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 311 sdrc_block_contents.rfr_ctrl_0 = 312 sdrc_read_reg(SDRC_RFR_CTRL_0); 313 sdrc_block_contents.cs_1 = 0x0; 314 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 315 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 316 sdrc_block_contents.emr_1_1 = 0x0; 317 sdrc_block_contents.emr_2_1 = 0x0; 318 sdrc_block_contents.emr_3_1 = 0x0; 319 sdrc_block_contents.actim_ctrla_1 = 320 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 321 sdrc_block_contents.actim_ctrlb_1 = 322 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 323 sdrc_block_contents.rfr_ctrl_1 = 324 sdrc_read_reg(SDRC_RFR_CTRL_1); 325 sdrc_block_contents.dcdl_1_ctrl = 0x0; 326 sdrc_block_contents.dcdl_2_ctrl = 0x0; 327 sdrc_block_contents.flags = 0x0; 328 sdrc_block_contents.block_size = 0x0; 329 330 arm_context_addr = __pa_symbol(omap3_arm_context); 331 332 /* Copy all the contents to the scratchpad location */ 333 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 334 memcpy_toio(scratchpad_address, &scratchpad_contents, 335 sizeof(scratchpad_contents)); 336 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 337 memcpy_toio(scratchpad_address + 338 scratchpad_contents.prcm_block_offset, 339 &prcm_block_contents, sizeof(prcm_block_contents)); 340 memcpy_toio(scratchpad_address + 341 scratchpad_contents.sdrc_block_offset, 342 &sdrc_block_contents, sizeof(sdrc_block_contents)); 343 /* 344 * Copies the address of the location in SDRAM where ARM 345 * registers get saved during a MPU OFF transition. 346 */ 347 memcpy_toio(scratchpad_address + 348 scratchpad_contents.sdrc_block_offset + 349 sizeof(sdrc_block_contents), &arm_context_addr, 4); 350} 351 352void omap3_control_save_context(void) 353{ 354 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 355 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 356 control_context.mem_dftrw0 = 357 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 358 control_context.mem_dftrw1 = 359 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 360 control_context.msuspendmux_0 = 361 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 362 control_context.msuspendmux_1 = 363 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 364 control_context.msuspendmux_2 = 365 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 366 control_context.msuspendmux_3 = 367 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 368 control_context.msuspendmux_4 = 369 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 370 control_context.msuspendmux_5 = 371 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 372 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 373 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 374 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 375 control_context.iva2_bootaddr = 376 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 377 control_context.iva2_bootmod = 378 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 379 control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); 380 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 381 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 382 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 383 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 384 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 385 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 386 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 387 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 388 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 389 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 390 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 391 control_context.dss_dpll_spreading = 392 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 393 control_context.core_dpll_spreading = 394 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 395 control_context.per_dpll_spreading = 396 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 397 control_context.usbhost_dpll_spreading = 398 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 399 control_context.pbias_lite = 400 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 401 control_context.temp_sensor = 402 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 403 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 404 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 405 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 406 control_context.padconf_sys_nirq = 407 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 408} 409 410void omap3_control_restore_context(void) 411{ 412 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 413 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 414 omap_ctrl_writel(control_context.mem_dftrw0, 415 OMAP343X_CONTROL_MEM_DFTRW0); 416 omap_ctrl_writel(control_context.mem_dftrw1, 417 OMAP343X_CONTROL_MEM_DFTRW1); 418 omap_ctrl_writel(control_context.msuspendmux_0, 419 OMAP2_CONTROL_MSUSPENDMUX_0); 420 omap_ctrl_writel(control_context.msuspendmux_1, 421 OMAP2_CONTROL_MSUSPENDMUX_1); 422 omap_ctrl_writel(control_context.msuspendmux_2, 423 OMAP2_CONTROL_MSUSPENDMUX_2); 424 omap_ctrl_writel(control_context.msuspendmux_3, 425 OMAP2_CONTROL_MSUSPENDMUX_3); 426 omap_ctrl_writel(control_context.msuspendmux_4, 427 OMAP2_CONTROL_MSUSPENDMUX_4); 428 omap_ctrl_writel(control_context.msuspendmux_5, 429 OMAP2_CONTROL_MSUSPENDMUX_5); 430 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 431 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 432 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 433 omap_ctrl_writel(control_context.iva2_bootaddr, 434 OMAP343X_CONTROL_IVA2_BOOTADDR); 435 omap_ctrl_writel(control_context.iva2_bootmod, 436 OMAP343X_CONTROL_IVA2_BOOTMOD); 437 omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL); 438 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 439 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 440 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 441 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 442 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 443 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 444 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 445 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 446 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 447 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 448 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 449 omap_ctrl_writel(control_context.dss_dpll_spreading, 450 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 451 omap_ctrl_writel(control_context.core_dpll_spreading, 452 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 453 omap_ctrl_writel(control_context.per_dpll_spreading, 454 OMAP343X_CONTROL_PER_DPLL_SPREADING); 455 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 456 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 457 omap_ctrl_writel(control_context.pbias_lite, 458 OMAP343X_CONTROL_PBIAS_LITE); 459 omap_ctrl_writel(control_context.temp_sensor, 460 OMAP343X_CONTROL_TEMP_SENSOR); 461 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 462 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 463 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 464 omap_ctrl_writel(control_context.padconf_sys_nirq, 465 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 466} 467 468void omap3630_ctrl_disable_rta(void) 469{ 470 if (!cpu_is_omap3630()) 471 return; 472 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 473} 474 475/** 476 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 477 * 478 * Tell the SCM to start saving the padconf registers, then wait for 479 * the process to complete. Returns 0 unconditionally, although it 480 * should also eventually be able to return -ETIMEDOUT, if the save 481 * does not complete. 482 * 483 * XXX This function is missing a timeout. What should it be? 484 */ 485int omap3_ctrl_save_padconf(void) 486{ 487 u32 cpo; 488 489 /* Save the padconf registers */ 490 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 491 cpo |= START_PADCONF_SAVE; 492 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 493 494 /* wait for the save to complete */ 495 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 496 & PADCONF_SAVE_DONE)) 497 udelay(1); 498 499 return 0; 500} 501 502/** 503 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 504 * 505 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 506 * force disable IVA2 so that it does not prevent any low-power states. 507 */ 508static void __init omap3_ctrl_set_iva_bootmode_idle(void) 509{ 510 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 511 OMAP343X_CONTROL_IVA2_BOOTMOD); 512} 513 514/** 515 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 516 * 517 * Sets up the pads controlling the stacked modem in such way that the 518 * device can enter idle. 519 */ 520static void __init omap3_ctrl_setup_d2d_padconf(void) 521{ 522 u16 mask, padconf; 523 524 /* 525 * In a stand alone OMAP3430 where there is not a stacked 526 * modem for the D2D Idle Ack and D2D MStandby must be pulled 527 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 528 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 529 */ 530 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 531 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 532 padconf |= mask; 533 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 534 535 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 536 padconf |= mask; 537 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 538} 539 540/** 541 * omap3_ctrl_init - does static initializations for control module 542 * 543 * Initializes system control module. This sets up the sysconfig autoidle, 544 * and sets up modem and iva2 so that they can be idled properly. 545 */ 546void __init omap3_ctrl_init(void) 547{ 548 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 549 550 omap3_ctrl_set_iva_bootmode_idle(); 551 552 omap3_ctrl_setup_d2d_padconf(); 553} 554#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 555 556static unsigned long am43xx_control_reg_offsets[] = { 557 AM33XX_CONTROL_SYSCONFIG_OFFSET, 558 AM33XX_CONTROL_STATUS_OFFSET, 559 AM43XX_CONTROL_MPU_L2_CTRL_OFFSET, 560 AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET, 561 AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET, 562 AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET, 563 AM33XX_CONTROL_BANDGAP_CTRL_OFFSET, 564 AM33XX_CONTROL_BANDGAP_TRIM_OFFSET, 565 AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET, 566 AM33XX_CONTROL_MOSC_CTRL_OFFSET, 567 AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET, 568 AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET, 569 AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET, 570 AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET, 571 AM33XX_CONTROL_TPTC_CFG_OFFSET, 572 AM33XX_CONTROL_USB_CTRL0_OFFSET, 573 AM33XX_CONTROL_USB_CTRL1_OFFSET, 574 AM43XX_CONTROL_USB_CTRL2_OFFSET, 575 AM43XX_CONTROL_GMII_SEL_OFFSET, 576 AM43XX_CONTROL_MPUSS_CTRL_OFFSET, 577 AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET, 578 AM43XX_CONTROL_PWMSS_CTRL_OFFSET, 579 AM33XX_CONTROL_MREQPRIO_0_OFFSET, 580 AM33XX_CONTROL_MREQPRIO_1_OFFSET, 581 AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET, 582 AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET, 583 AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET, 584 AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET, 585 AM33XX_CONTROL_SMRT_CTRL_OFFSET, 586 AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET, 587 AM43XX_CONTROL_CQDETECT_STS_OFFSET, 588 AM43XX_CONTROL_CQDETECT_STS2_OFFSET, 589 AM43XX_CONTROL_VTP_CTRL_OFFSET, 590 AM33XX_CONTROL_VREF_CTRL_OFFSET, 591 AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET, 592 AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET, 593 AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET, 594 AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET, 595 AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET, 596 AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET, 597 AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET, 598 AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET, 599 AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET, 600 AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET, 601 AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET, 602 AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET, 603 AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET, 604 AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET, 605 AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET, 606 AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET, 607 AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET, 608 AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET, 609 AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET, 610 AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET, 611 AM33XX_CONTROL_RESET_ISO_OFFSET, 612}; 613 614static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)]; 615 616/** 617 * am43xx_control_save_context - Save the wakeup domain registers 618 * 619 * Save the wkup domain registers 620 */ 621static void am43xx_control_save_context(void) 622{ 623 int i; 624 625 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 626 am33xx_control_vals[i] = 627 omap_ctrl_readl(am43xx_control_reg_offsets[i]); 628} 629 630/** 631 * am43xx_control_restore_context - Restore the wakeup domain registers 632 * 633 * Restore the wkup domain registers 634 */ 635static void am43xx_control_restore_context(void) 636{ 637 int i; 638 639 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 640 omap_ctrl_writel(am33xx_control_vals[i], 641 am43xx_control_reg_offsets[i]); 642} 643 644static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v) 645{ 646 switch (cmd) { 647 case CPU_CLUSTER_PM_ENTER: 648 if (enable_off_mode) 649 am43xx_control_save_context(); 650 break; 651 case CPU_CLUSTER_PM_EXIT: 652 if (enable_off_mode) 653 am43xx_control_restore_context(); 654 break; 655 } 656 657 return NOTIFY_OK; 658} 659 660struct control_init_data { 661 int index; 662 void __iomem *mem; 663 s16 offset; 664}; 665 666static struct control_init_data ctrl_data = { 667 .index = TI_CLKM_CTRL, 668}; 669 670static const struct control_init_data omap2_ctrl_data = { 671 .index = TI_CLKM_CTRL, 672 .offset = -OMAP2_CONTROL_GENERAL, 673}; 674 675static const struct control_init_data ctrl_aux_data = { 676 .index = TI_CLKM_CTRL_AUX, 677}; 678 679static const struct of_device_id omap_scrm_dt_match_table[] = { 680 { .compatible = "ti,am3-scm", .data = &ctrl_data }, 681 { .compatible = "ti,am4-scm", .data = &ctrl_data }, 682 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, 683 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, 684 { .compatible = "ti,dm814-scm", .data = &ctrl_data }, 685 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 686 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, 687 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, 688 { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data }, 689 { .compatible = "ti,dra7-scm-core", .data = &ctrl_data }, 690 { } 691}; 692 693/** 694 * omap2_control_base_init - initialize iomappings for the control driver 695 * 696 * Detects and initializes the iomappings for the control driver, based 697 * on the DT data. Returns 0 in success, negative error value 698 * otherwise. 699 */ 700int __init omap2_control_base_init(void) 701{ 702 struct device_node *np; 703 const struct of_device_id *match; 704 struct control_init_data *data; 705 void __iomem *mem; 706 707 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 708 data = (struct control_init_data *)match->data; 709 710 mem = of_iomap(np, 0); 711 if (!mem) { 712 of_node_put(np); 713 return -ENOMEM; 714 } 715 716 if (data->index == TI_CLKM_CTRL) { 717 omap2_ctrl_base = mem; 718 omap2_ctrl_offset = data->offset; 719 } 720 721 data->mem = mem; 722 } 723 724 return 0; 725} 726 727/** 728 * omap_control_init - low level init for the control driver 729 * 730 * Initializes the low level clock infrastructure for control driver. 731 * Returns 0 in success, negative error value in failure. 732 */ 733int __init omap_control_init(void) 734{ 735 struct device_node *np, *scm_conf; 736 const struct of_device_id *match; 737 const struct omap_prcm_init_data *data; 738 int ret; 739 struct regmap *syscon; 740 static struct notifier_block nb; 741 742 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 743 data = match->data; 744 745 /* 746 * Check if we have scm_conf node, if yes, use this to 747 * access clock registers. 748 */ 749 scm_conf = of_get_child_by_name(np, "scm_conf"); 750 751 if (scm_conf) { 752 syscon = syscon_node_to_regmap(scm_conf); 753 754 if (IS_ERR(syscon)) { 755 ret = PTR_ERR(syscon); 756 goto of_node_put; 757 } 758 759 if (of_get_child_by_name(scm_conf, "clocks")) { 760 ret = omap2_clk_provider_init(scm_conf, 761 data->index, 762 syscon, NULL); 763 if (ret) 764 goto of_node_put; 765 } 766 } else { 767 /* No scm_conf found, direct access */ 768 ret = omap2_clk_provider_init(np, data->index, NULL, 769 data->mem); 770 if (ret) 771 goto of_node_put; 772 } 773 } 774 775 /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */ 776 if (soc_is_am43xx()) { 777 nb.notifier_call = cpu_notifier; 778 cpu_pm_register_notifier(&nb); 779 } 780 781 return 0; 782 783of_node_put: 784 of_node_put(np); 785 return ret; 786 787} 788