1283625Sdim// SPDX-License-Identifier: GPL-2.0-only 2283625Sdim/* 3353358Sdim * OMAP4 CM instance functions 4353358Sdim * 5353358Sdim * Copyright (C) 2009 Nokia Corporation 6283625Sdim * Copyright (C) 2008-2011 Texas Instruments, Inc. 7283625Sdim * Paul Walmsley 8283625Sdim * Rajendra Nayak <rnayak@ti.com> 9283625Sdim * 10283625Sdim * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, 11283625Sdim * or CM2 hardware modules. For example, the EMU_CM CM instance is in 12283625Sdim * the PRM hardware module. What a mess... 13283625Sdim */ 14283625Sdim 15283625Sdim#include <linux/kernel.h> 16321369Sdim#include <linux/types.h> 17321369Sdim#include <linux/errno.h> 18283625Sdim#include <linux/err.h> 19283625Sdim#include <linux/io.h> 20283625Sdim 21283625Sdim#include "clockdomain.h" 22283625Sdim#include "cm.h" 23283625Sdim#include "cm1_44xx.h" 24283625Sdim#include "cm2_44xx.h" 25283625Sdim#include "cm44xx.h" 26283625Sdim#include "cm-regbits-34xx.h" 27283625Sdim#include "prcm44xx.h" 28283625Sdim#include "prm44xx.h" 29283625Sdim#include "prcm_mpu44xx.h" 30283625Sdim#include "prcm-common.h" 31283625Sdim 32341825Sdim#define OMAP4430_IDLEST_SHIFT 16 33283625Sdim#define OMAP4430_IDLEST_MASK (0x3 << 16) 34341825Sdim#define OMAP4430_CLKTRCTRL_SHIFT 0 35341825Sdim#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 36341825Sdim#define OMAP4430_MODULEMODE_SHIFT 0 37341825Sdim#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 38341825Sdim 39344779Sdim/* 40344779Sdim * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 41344779Sdim * 42344779Sdim * 0x0 func: Module is fully functional, including OCP 43344779Sdim * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 44344779Sdim * abortion 45344779Sdim * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if 46341825Sdim * using separate functional clock 47341825Sdim * 0x3 disabled: Module is disabled and cannot be accessed 48341825Sdim * 49341825Sdim */ 50341825Sdim#define CLKCTRL_IDLEST_FUNCTIONAL 0x0 51341825Sdim#define CLKCTRL_IDLEST_INTRANSITION 0x1 52341825Sdim#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 53341825Sdim#define CLKCTRL_IDLEST_DISABLED 0x3 54341825Sdim 55341825Sdimstatic struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 56283625Sdim 57283625Sdim/** 58314564Sdim * omap_cm_base_init - Populates the cm partitions 59341825Sdim * 60283625Sdim * Populates the base addresses of the _cm_bases 61341825Sdim * array used for read/write of cm module registers. 62283625Sdim */ 63341825Sdimstatic void omap_cm_base_init(void) 64353358Sdim{ 65341825Sdim memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base)); 66283625Sdim memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); 67283625Sdim memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base)); 68283625Sdim memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base, 69283625Sdim sizeof(prcm_mpu_base)); 70283625Sdim} 71283625Sdim 72283625Sdim/* Private functions */ 73283625Sdim 74283625Sdimstatic u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); 75283625Sdim 76283625Sdim/** 77283625Sdim * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 78283625Sdim * @part: PRCM partition ID that the CM_CLKCTRL register exists in 79283625Sdim * @inst: CM instance register offset (*_INST macro) 80283625Sdim * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 81283625Sdim * 82283625Sdim * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to 83283625Sdim * bit 0. 84283625Sdim */ 85283625Sdimstatic u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) 86283625Sdim{ 87283625Sdim u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 88296417Sdim v &= OMAP4430_IDLEST_MASK; 89283625Sdim v >>= OMAP4430_IDLEST_SHIFT; 90283625Sdim return v; 91283625Sdim} 92283625Sdim 93283625Sdim/** 94283625Sdim * _is_module_ready - can module registers be accessed without causing an abort? 95283625Sdim * @part: PRCM partition ID that the CM_CLKCTRL register exists in 96283625Sdim * @inst: CM instance register offset (*_INST macro) 97283625Sdim * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 98296417Sdim * 99283625Sdim * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either 100283625Sdim * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. 101283625Sdim */ 102283625Sdimstatic bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) 103283625Sdim{ 104283625Sdim u32 v; 105283625Sdim 106296417Sdim v = _clkctrl_idlest(part, inst, clkctrl_offs); 107283625Sdim 108283625Sdim return (v == CLKCTRL_IDLEST_FUNCTIONAL || 109283625Sdim v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; 110283625Sdim} 111341825Sdim 112341825Sdim/* Read a register in a CM instance */ 113341825Sdimstatic u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) 114341825Sdim{ 115341825Sdim BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 116341825Sdim part == OMAP4430_INVALID_PRCM_PARTITION || 117341825Sdim !_cm_bases[part].va); 118341825Sdim return readl_relaxed(_cm_bases[part].va + inst + idx); 119341825Sdim} 120341825Sdim 121341825Sdim/* Write into a register in a CM instance */ 122283625Sdimstatic void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) 123283625Sdim{ 124283625Sdim BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 125283625Sdim part == OMAP4430_INVALID_PRCM_PARTITION || 126296417Sdim !_cm_bases[part].va); 127283625Sdim writel_relaxed(val, _cm_bases[part].va + inst + idx); 128283625Sdim} 129283625Sdim 130344779Sdim/* Read-modify-write a register in CM1. Caller must lock */ 131344779Sdimstatic u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, 132344779Sdim s16 idx) 133344779Sdim{ 134344779Sdim u32 v; 135344779Sdim 136344779Sdim v = omap4_cminst_read_inst_reg(part, inst, idx); 137283625Sdim v &= ~mask; 138283625Sdim v |= bits; 139283625Sdim omap4_cminst_write_inst_reg(v, part, inst, idx); 140283625Sdim 141283625Sdim return v; 142283625Sdim} 143341825Sdim 144341825Sdimstatic u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) 145341825Sdim{ 146341825Sdim return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); 147341825Sdim} 148341825Sdim 149341825Sdimstatic u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, 150341825Sdim s16 idx) 151341825Sdim{ 152341825Sdim return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); 153341825Sdim} 154341825Sdim 155341825Sdimstatic u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) 156341825Sdim{ 157341825Sdim u32 v; 158341825Sdim 159341825Sdim v = omap4_cminst_read_inst_reg(part, inst, idx); 160341825Sdim v &= mask; 161341825Sdim v >>= __ffs(mask); 162341825Sdim 163341825Sdim return v; 164341825Sdim} 165341825Sdim 166341825Sdim/* 167341825Sdim * 168341825Sdim */ 169341825Sdim 170341825Sdim/** 171341825Sdim * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield 172341825Sdim * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) 173341825Sdim * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 174341825Sdim * @inst: CM instance register offset (*_INST macro) 175341825Sdim * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 176341825Sdim * 177341825Sdim * @c must be the unshifted value for CLKTRCTRL - i.e., this function 178341825Sdim * will handle the shift itself. 179341825Sdim */ 180341825Sdimstatic void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) 181341825Sdim{ 182341825Sdim u32 v; 183341825Sdim 184341825Sdim v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 185341825Sdim v &= ~OMAP4430_CLKTRCTRL_MASK; 186341825Sdim v |= c << OMAP4430_CLKTRCTRL_SHIFT; 187341825Sdim omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 188341825Sdim} 189353358Sdim 190309124Sdim/** 191353358Sdim * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? 192353358Sdim * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in 193309124Sdim * @inst: CM instance register offset (*_INST macro) 194309124Sdim * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 195283625Sdim * 196283625Sdim * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) 197353358Sdim * is in hardware-supervised idle mode, or 0 otherwise. 198283625Sdim */ 199283625Sdimstatic bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) 200309124Sdim{ 201309124Sdim u32 v; 202309124Sdim 203353358Sdim v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); 204283625Sdim v &= OMAP4430_CLKTRCTRL_MASK; 205283625Sdim v >>= OMAP4430_CLKTRCTRL_SHIFT; 206283625Sdim 207283625Sdim return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; 208285181Sdim} 209285181Sdim 210283625Sdim/** 211283625Sdim * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode 212296417Sdim * @part: PRCM partition ID that the clockdomain registers exist in 213283625Sdim * @inst: CM instance register offset (*_INST macro) 214341825Sdim * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 215341825Sdim * 216341825Sdim * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 217341825Sdim * hardware-supervised idle mode. No return value. 218341825Sdim */ 219283625Sdimstatic void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) 220283625Sdim{ 221283625Sdim _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); 222283625Sdim} 223283625Sdim 224283625Sdim/** 225283625Sdim * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode 226283625Sdim * @part: PRCM partition ID that the clockdomain registers exist in 227283625Sdim * @inst: CM instance register offset (*_INST macro) 228296417Sdim * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 229296417Sdim * 230341825Sdim * Put a clockdomain referred to by (@part, @inst, @cdoffs) into 231341825Sdim * software-supervised idle mode, i.e., controlled manually by the 232341825Sdim * Linux OMAP clockdomain code. No return value. 233341825Sdim */ 234341825Sdimstatic void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) 235283625Sdim{ 236283625Sdim _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); 237283625Sdim} 238283625Sdim 239296417Sdim/** 240296417Sdim * omap4_cminst_clkdm_force_wakeup - try to take a clockdomain out of idle 241283625Sdim * @part: PRCM partition ID that the clockdomain registers exist in 242283625Sdim * @inst: CM instance register offset (*_INST macro) 243283625Sdim * @cdoffs: Clockdomain register offset (*_CDOFFS macro) 244283625Sdim * 245283625Sdim * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, 246283625Sdim * waking it up. No return value. 247283625Sdim */ 248341825Sdimstatic void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) 249341825Sdim{ 250341825Sdim _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); 251283625Sdim} 252283625Sdim 253283625Sdim/* 254283625Sdim * 255283625Sdim */ 256283625Sdim 257309124Sdimstatic void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) 258309124Sdim{ 259309124Sdim _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); 260309124Sdim} 261309124Sdim 262309124Sdim/** 263283625Sdim * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state 264283625Sdim * @part: PRCM partition ID that the CM_CLKCTRL register exists in 265283625Sdim * @inst: CM instance register offset (*_INST macro) 266283625Sdim * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 267283625Sdim * @bit_shift: bit shift for the register, ignored for OMAP4+ 268283625Sdim * 269283625Sdim * Wait for the module IDLEST to be functional. If the idle state is in any 270283625Sdim * the non functional state (trans, idle or disabled), module and thus the 271283625Sdim * sysconfig cannot be accessed and will probably lead to an "imprecise 272283625Sdim * external abort" 273296417Sdim */ 274296417Sdimstatic int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, 275296417Sdim u8 bit_shift) 276283625Sdim{ 277283625Sdim int i = 0; 278283625Sdim 279283625Sdim omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), 280283625Sdim MAX_MODULE_READY_TIME, i); 281341825Sdim 282353358Sdim return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 283309124Sdim} 284283625Sdim 285283625Sdim/** 286353358Sdim * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' 287360784Sdim * state 288360784Sdim * @part: PRCM partition ID that the CM_CLKCTRL register exists in 289360784Sdim * @inst: CM instance register offset (*_INST macro) 290341825Sdim * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 291341825Sdim * @bit_shift: Bit shift for the register, ignored for OMAP4+ 292341825Sdim * 293341825Sdim * Wait for the module IDLEST to be disabled. Some PRCM transition, 294360784Sdim * like reset assertion or parent clock de-activation must wait the 295283625Sdim * module to be fully disabled. 296283625Sdim */ 297309124Sdimstatic int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, 298283625Sdim u8 bit_shift) 299283625Sdim{ 300283625Sdim int i = 0; 301283625Sdim 302283625Sdim omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == 303283625Sdim CLKCTRL_IDLEST_DISABLED), 304283625Sdim MAX_MODULE_DISABLE_TIME, i); 305283625Sdim 306 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY; 307} 308 309/** 310 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL 311 * @mode: Module mode (SW or HW) 312 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 313 * @inst: CM instance register offset (*_INST macro) 314 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 315 * 316 * No return value. 317 */ 318static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, 319 u16 clkctrl_offs) 320{ 321 u32 v; 322 323 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 324 v &= ~OMAP4430_MODULEMODE_MASK; 325 v |= mode << OMAP4430_MODULEMODE_SHIFT; 326 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 327} 328 329/** 330 * omap4_cminst_module_disable - Disable the module inside CLKCTRL 331 * @part: PRCM partition ID that the CM_CLKCTRL register exists in 332 * @inst: CM instance register offset (*_INST macro) 333 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) 334 * 335 * No return value. 336 */ 337static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) 338{ 339 u32 v; 340 341 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); 342 v &= ~OMAP4430_MODULEMODE_MASK; 343 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); 344} 345 346/* 347 * Clockdomain low-level functions 348 */ 349 350static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, 351 struct clockdomain *clkdm2) 352{ 353 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), 354 clkdm1->prcm_partition, 355 clkdm1->cm_inst, clkdm1->clkdm_offs + 356 OMAP4_CM_STATICDEP); 357 return 0; 358} 359 360static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, 361 struct clockdomain *clkdm2) 362{ 363 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), 364 clkdm1->prcm_partition, 365 clkdm1->cm_inst, clkdm1->clkdm_offs + 366 OMAP4_CM_STATICDEP); 367 return 0; 368} 369 370static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, 371 struct clockdomain *clkdm2) 372{ 373 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, 374 clkdm1->cm_inst, 375 clkdm1->clkdm_offs + 376 OMAP4_CM_STATICDEP, 377 (1 << clkdm2->dep_bit)); 378} 379 380static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) 381{ 382 struct clkdm_dep *cd; 383 u32 mask = 0; 384 385 if (!clkdm->prcm_partition) 386 return 0; 387 388 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 389 if (!cd->clkdm) 390 continue; /* only happens if data is erroneous */ 391 392 mask |= 1 << cd->clkdm->dep_bit; 393 cd->wkdep_usecount = 0; 394 } 395 396 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 397 clkdm->cm_inst, clkdm->clkdm_offs + 398 OMAP4_CM_STATICDEP); 399 return 0; 400} 401 402static int omap4_clkdm_sleep(struct clockdomain *clkdm) 403{ 404 if (clkdm->flags & CLKDM_CAN_HWSUP) 405 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 406 clkdm->cm_inst, 407 clkdm->clkdm_offs); 408 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) 409 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 410 clkdm->cm_inst, 411 clkdm->clkdm_offs); 412 else 413 return -EINVAL; 414 415 return 0; 416} 417 418static int omap4_clkdm_wakeup(struct clockdomain *clkdm) 419{ 420 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, 421 clkdm->cm_inst, clkdm->clkdm_offs); 422 return 0; 423} 424 425static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) 426{ 427 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, 428 clkdm->cm_inst, clkdm->clkdm_offs); 429} 430 431static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 432{ 433 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 434 omap4_clkdm_wakeup(clkdm); 435 else 436 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 437 clkdm->cm_inst, 438 clkdm->clkdm_offs); 439} 440 441static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 442{ 443 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 444 return omap4_clkdm_wakeup(clkdm); 445 446 return 0; 447} 448 449static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) 450{ 451 bool hwsup = false; 452 453 if (!clkdm->prcm_partition) 454 return 0; 455 456 /* 457 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has 458 * more details on the unpleasant problem this is working 459 * around 460 */ 461 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && 462 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { 463 omap4_clkdm_allow_idle(clkdm); 464 return 0; 465 } 466 467 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 468 clkdm->cm_inst, clkdm->clkdm_offs); 469 470 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) 471 omap4_clkdm_sleep(clkdm); 472 473 return 0; 474} 475 476static u32 omap4_cminst_xlate_clkctrl(u8 part, u16 inst, u16 offset) 477{ 478 return _cm_bases[part].pa + inst + offset; 479} 480 481/** 482 * omap4_clkdm_save_context - Save the clockdomain modulemode context 483 * @clkdm: The clockdomain pointer whose context needs to be saved 484 * 485 * Save the clockdomain modulemode context. 486 */ 487static int omap4_clkdm_save_context(struct clockdomain *clkdm) 488{ 489 clkdm->context = omap4_cminst_read_inst_reg(clkdm->prcm_partition, 490 clkdm->cm_inst, 491 clkdm->clkdm_offs + 492 OMAP4_CM_CLKSTCTRL); 493 clkdm->context &= OMAP4430_MODULEMODE_MASK; 494 return 0; 495} 496 497/** 498 * omap4_clkdm_restore_context - Restore the clockdomain modulemode context 499 * @clkdm: The clockdomain pointer whose context needs to be restored 500 * 501 * Restore the clockdomain modulemode context. 502 */ 503static int omap4_clkdm_restore_context(struct clockdomain *clkdm) 504{ 505 switch (clkdm->context) { 506 case OMAP34XX_CLKSTCTRL_DISABLE_AUTO: 507 omap4_clkdm_deny_idle(clkdm); 508 break; 509 case OMAP34XX_CLKSTCTRL_FORCE_SLEEP: 510 omap4_clkdm_sleep(clkdm); 511 break; 512 case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP: 513 omap4_clkdm_wakeup(clkdm); 514 break; 515 case OMAP34XX_CLKSTCTRL_ENABLE_AUTO: 516 omap4_clkdm_allow_idle(clkdm); 517 break; 518 } 519 return 0; 520} 521 522struct clkdm_ops omap4_clkdm_operations = { 523 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 524 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 525 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, 526 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 527 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, 528 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, 529 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, 530 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, 531 .clkdm_sleep = omap4_clkdm_sleep, 532 .clkdm_wakeup = omap4_clkdm_wakeup, 533 .clkdm_allow_idle = omap4_clkdm_allow_idle, 534 .clkdm_deny_idle = omap4_clkdm_deny_idle, 535 .clkdm_clk_enable = omap4_clkdm_clk_enable, 536 .clkdm_clk_disable = omap4_clkdm_clk_disable, 537 .clkdm_save_context = omap4_clkdm_save_context, 538 .clkdm_restore_context = omap4_clkdm_restore_context, 539}; 540 541struct clkdm_ops am43xx_clkdm_operations = { 542 .clkdm_sleep = omap4_clkdm_sleep, 543 .clkdm_wakeup = omap4_clkdm_wakeup, 544 .clkdm_allow_idle = omap4_clkdm_allow_idle, 545 .clkdm_deny_idle = omap4_clkdm_deny_idle, 546 .clkdm_clk_enable = omap4_clkdm_clk_enable, 547 .clkdm_clk_disable = omap4_clkdm_clk_disable, 548}; 549 550static const struct cm_ll_data omap4xxx_cm_ll_data = { 551 .wait_module_ready = &omap4_cminst_wait_module_ready, 552 .wait_module_idle = &omap4_cminst_wait_module_idle, 553 .module_enable = &omap4_cminst_module_enable, 554 .module_disable = &omap4_cminst_module_disable, 555 .xlate_clkctrl = &omap4_cminst_xlate_clkctrl, 556}; 557 558int __init omap4_cm_init(const struct omap_prcm_init_data *data) 559{ 560 omap_cm_base_init(); 561 562 return cm_register(&omap4xxx_cm_ll_data); 563} 564 565static void __exit omap4_cm_exit(void) 566{ 567 cm_unregister(&omap4xxx_cm_ll_data); 568} 569__exitcall(omap4_cm_exit); 570