1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-mv78xx0/irq.c
4 *
5 * MV78xx0 IRQ handling.
6 */
7#include <linux/gpio.h>
8#include <linux/kernel.h>
9#include <linux/irq.h>
10#include <linux/io.h>
11#include <asm/exception.h>
12#include <plat/orion-gpio.h>
13#include <plat/irq.h>
14#include "bridge-regs.h"
15#include "common.h"
16
17static int __initdata gpio0_irqs[4] = {
18	IRQ_MV78XX0_GPIO_0_7,
19	IRQ_MV78XX0_GPIO_8_15,
20	IRQ_MV78XX0_GPIO_16_23,
21	IRQ_MV78XX0_GPIO_24_31,
22};
23
24static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
25
26static asmlinkage void
27__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
28{
29	u32 stat;
30
31	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
32	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
33	if (stat) {
34		unsigned int hwirq = __fls(stat);
35		handle_IRQ(hwirq, regs);
36		return;
37	}
38	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
39	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
40	if (stat) {
41		unsigned int hwirq = 32 + __fls(stat);
42		handle_IRQ(hwirq, regs);
43		return;
44	}
45	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
46	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
47	if (stat) {
48		unsigned int hwirq = 64 + __fls(stat);
49		handle_IRQ(hwirq, regs);
50		return;
51	}
52}
53
54void __init mv78xx0_init_irq(void)
55{
56	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
57	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
58	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
59
60	set_handle_irq(mv78xx0_legacy_handle_irq);
61
62	/*
63	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
64	 * registers for core #1 are at an offset of 0x18 from those of
65	 * core #0.)
66	 */
67	orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
68			IRQ_MV78XX0_GPIO_START, gpio0_irqs);
69}
70