133965Sjdp// SPDX-License-Identifier: GPL-2.0 233965Sjdp/* 3218822Sdim * Device Tree Source for the r8a73a4 SoC 460484Sobrien * 533965Sjdp * Copyright (C) 2013 Renesas Solutions Corp. 633965Sjdp * Copyright (C) 2013 Magnus Damm 733965Sjdp */ 833965Sjdp 933965Sjdp#include <dt-bindings/clock/r8a73a4-clock.h> 1033965Sjdp#include <dt-bindings/interrupt-controller/arm-gic.h> 1133965Sjdp#include <dt-bindings/interrupt-controller/irq.h> 1233965Sjdp 1333965Sjdp/ { 1433965Sjdp compatible = "renesas,r8a73a4"; 1533965Sjdp interrupt-parent = <&gic>; 1633965Sjdp #address-cells = <2>; 1733965Sjdp #size-cells = <2>; 1833965Sjdp 19218822Sdim cpus { 20218822Sdim #address-cells = <1>; 2133965Sjdp #size-cells = <0>; 2233965Sjdp 2360484Sobrien cpu0: cpu@0 { 2433965Sjdp device_type = "cpu"; 2533965Sjdp compatible = "arm,cortex-a15"; 2633965Sjdp reg = <0>; 2733965Sjdp clocks = <&cpg_clocks R8A73A4_CLK_Z>; 2833965Sjdp clock-frequency = <1500000000>; 29130561Sobrien power-domains = <&pd_a2sl>; 3060484Sobrien next-level-cache = <&L2_CA15>; 3133965Sjdp }; 3260484Sobrien 3333965Sjdp L2_CA15: cache-controller-0 { 3460484Sobrien compatible = "cache"; 3560484Sobrien clocks = <&cpg_clocks R8A73A4_CLK_Z>; 3660484Sobrien power-domains = <&pd_a3sm>; 37104834Sobrien cache-unified; 38104834Sobrien cache-level = <2>; 3933965Sjdp }; 4060484Sobrien 4133965Sjdp L2_CA7: cache-controller-1 { 4233965Sjdp compatible = "cache"; 4333965Sjdp clocks = <&cpg_clocks R8A73A4_CLK_Z2>; 4433965Sjdp power-domains = <&pd_a3km>; 4533965Sjdp cache-unified; 4633965Sjdp cache-level = <2>; 4733965Sjdp }; 4833965Sjdp }; 4933965Sjdp 5060484Sobrien ptm { 5160484Sobrien compatible = "arm,coresight-etm3x"; 5260484Sobrien power-domains = <&pd_d4>; 53130561Sobrien }; 5433965Sjdp 55104834Sobrien timer { 56104834Sobrien compatible = "arm,armv7-timer"; 57104834Sobrien interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5860484Sobrien <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 59243933Seadler <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6033965Sjdp <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6160484Sobrien }; 6260484Sobrien 6333965Sjdp tmu0: timer@e61e0000 { 6460484Sobrien compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 6589857Sobrien reg = <0 0xe61e0000 0 0x30>; 6689857Sobrien interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 6733965Sjdp <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 6833965Sjdp <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 6933965Sjdp interrupt-names = "tuni0", "tuni1", "tuni2"; 7033965Sjdp clocks = <&mstp1_clks R8A73A4_CLK_TMU0>; 7133965Sjdp clock-names = "fck"; 72130561Sobrien power-domains = <&pd_c5>; 73130561Sobrien status = "disabled"; 7433965Sjdp }; 7560484Sobrien 7633965Sjdp tmu3: timer@fff80000 { 7733965Sjdp compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 7833965Sjdp reg = <0 0xfff80000 0 0x30>; 7933965Sjdp interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 8033965Sjdp <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 8133965Sjdp <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 8233965Sjdp interrupt-names = "tuni0", "tuni1", "tuni2"; 8333965Sjdp clocks = <&mstp1_clks R8A73A4_CLK_TMU3>; 84243933Seadler clock-names = "fck"; 8533965Sjdp power-domains = <&pd_a3r>; 8633965Sjdp status = "disabled"; 87130561Sobrien }; 8833965Sjdp 8933965Sjdp dbsc1: memory-controller@e6790000 { 9033965Sjdp compatible = "renesas,dbsc-r8a73a4"; 9138889Sjdp reg = <0 0xe6790000 0 0x10000>; 9238889Sjdp power-domains = <&pd_a3bc>; 9338889Sjdp }; 9433965Sjdp 9533965Sjdp dbsc2: memory-controller@e67a0000 { 9633965Sjdp compatible = "renesas,dbsc-r8a73a4"; 9760484Sobrien reg = <0 0xe67a0000 0 0x10000>; 9860484Sobrien power-domains = <&pd_a3bc>; 9960484Sobrien }; 10060484Sobrien 10160484Sobrien i2c5: i2c@e60b0000 { 10260484Sobrien #address-cells = <1>; 10333965Sjdp #size-cells = <0>; 10460484Sobrien compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 10560484Sobrien reg = <0 0xe60b0000 0 0x428>; 10633965Sjdp interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 10789857Sobrien clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 10860484Sobrien power-domains = <&pd_a3sp>; 109130561Sobrien 11060484Sobrien status = "disabled"; 11133965Sjdp }; 11260484Sobrien 11360484Sobrien cmt1: timer@e6130000 { 11433965Sjdp compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; 11560484Sobrien reg = <0 0xe6130000 0 0x1004>; 11633965Sjdp interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 11733965Sjdp <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 11833965Sjdp <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 11960484Sobrien <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 120130561Sobrien <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 121130561Sobrien <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 12233965Sjdp <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 123130561Sobrien <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 12433965Sjdp clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 12589857Sobrien clock-names = "fck"; 12689857Sobrien power-domains = <&pd_c5>; 127130561Sobrien status = "disabled"; 128130561Sobrien }; 12989857Sobrien 13089857Sobrien irqc0: interrupt-controller@e61c0000 { 13189857Sobrien compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 132130561Sobrien #interrupt-cells = <2>; 13389857Sobrien interrupt-controller; 134218822Sdim reg = <0 0xe61c0000 0 0x200>; 135218822Sdim interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 13689857Sobrien <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 137218822Sdim <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 13889857Sobrien <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 13989857Sobrien <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 14089857Sobrien <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 141130561Sobrien <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 142130561Sobrien <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 14389857Sobrien <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 144130561Sobrien <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 14589857Sobrien <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 146218822Sdim <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 147218822Sdim <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 148130561Sobrien <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 149130561Sobrien <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 15089857Sobrien <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 151130561Sobrien <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 152130561Sobrien <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 153130561Sobrien <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 154218822Sdim <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 15589857Sobrien <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 156218822Sdim <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 157130561Sobrien <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 15889857Sobrien <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 159218822Sdim <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 160218822Sdim <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 16189857Sobrien <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 16289857Sobrien <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 16389857Sobrien <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 164218822Sdim <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 165218822Sdim <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 166218822Sdim <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 167130561Sobrien clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 168218822Sdim power-domains = <&pd_c4>; 169218822Sdim }; 170218822Sdim 171218822Sdim irqc1: interrupt-controller@e61c0200 { 172218822Sdim compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 173218822Sdim #interrupt-cells = <2>; 174218822Sdim interrupt-controller; 175218822Sdim reg = <0 0xe61c0200 0 0x200>; 176218822Sdim interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 177218822Sdim <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 178130561Sobrien <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 179130561Sobrien <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 180218822Sdim <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 181218822Sdim <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 182218822Sdim <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 18389857Sobrien <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 18489857Sobrien <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 18589857Sobrien <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 18689857Sobrien <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 187218822Sdim <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 188218822Sdim <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 189218822Sdim <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 190130561Sobrien <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 191130561Sobrien <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 192218822Sdim <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 193130561Sobrien <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 194218822Sdim <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 195218822Sdim <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 196218822Sdim <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 197218822Sdim <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 198130561Sobrien <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 199218822Sdim <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 200218822Sdim <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 201218822Sdim <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 202218822Sdim clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 203218822Sdim power-domains = <&pd_c4>; 204130561Sobrien }; 205218822Sdim 206218822Sdim pfc: pinctrl@e6050000 { 207130561Sobrien compatible = "renesas,pfc-r8a73a4"; 20889857Sobrien reg = <0 0xe6050000 0 0x9000>; 209104834Sobrien gpio-controller; 210104834Sobrien #gpio-cells = <2>; 211104834Sobrien gpio-ranges = 212104834Sobrien <&pfc 0 0 31>, <&pfc 32 32 9>, 213104834Sobrien <&pfc 64 64 22>, <&pfc 96 96 31>, 214104834Sobrien <&pfc 128 128 7>, <&pfc 160 160 19>, 215104834Sobrien <&pfc 192 192 31>, <&pfc 224 224 27>, 216104834Sobrien <&pfc 256 256 28>, <&pfc 288 288 21>, 217104834Sobrien <&pfc 320 320 10>; 218104834Sobrien interrupts-extended = 219104834Sobrien <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 220104834Sobrien <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 221104834Sobrien <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 222104834Sobrien <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 223104834Sobrien <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 224104834Sobrien <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 22589857Sobrien <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 22689857Sobrien <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 227243933Seadler <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 22889857Sobrien <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 22989857Sobrien <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 23089857Sobrien <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 23189857Sobrien <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 232243933Seadler <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 23389857Sobrien <&irqc1 24 0>, <&irqc1 25 0>; 23489857Sobrien power-domains = <&pd_c5>; 23589857Sobrien }; 23689857Sobrien 23789857Sobrien thermal@e61f0000 { 23889857Sobrien compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 23989857Sobrien reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 240243933Seadler <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 24189857Sobrien interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 24289857Sobrien clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 24389857Sobrien power-domains = <&pd_c5>; 24489857Sobrien }; 24560484Sobrien 24660484Sobrien i2c0: i2c@e6500000 { 24789857Sobrien #address-cells = <1>; 24833965Sjdp #size-cells = <0>; 249218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 250218822Sdim reg = <0 0xe6500000 0 0x428>; 251218822Sdim interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 252218822Sdim clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 253218822Sdim power-domains = <&pd_a3sp>; 254218822Sdim status = "disabled"; 255218822Sdim }; 256218822Sdim 257218822Sdim i2c1: i2c@e6510000 { 258218822Sdim #address-cells = <1>; 259218822Sdim #size-cells = <0>; 260218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 261218822Sdim reg = <0 0xe6510000 0 0x428>; 262218822Sdim interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 263218822Sdim clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 264218822Sdim power-domains = <&pd_a3sp>; 265218822Sdim status = "disabled"; 266218822Sdim }; 267218822Sdim 268218822Sdim i2c2: i2c@e6520000 { 269218822Sdim #address-cells = <1>; 270218822Sdim #size-cells = <0>; 271218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 272218822Sdim reg = <0 0xe6520000 0 0x428>; 273218822Sdim interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 274218822Sdim clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 275218822Sdim power-domains = <&pd_a3sp>; 276218822Sdim status = "disabled"; 277218822Sdim }; 278218822Sdim 279218822Sdim i2c3: i2c@e6530000 { 280218822Sdim #address-cells = <1>; 281218822Sdim #size-cells = <0>; 282218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 283218822Sdim reg = <0 0xe6530000 0 0x428>; 284218822Sdim interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 285218822Sdim clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 286218822Sdim power-domains = <&pd_a3sp>; 287218822Sdim status = "disabled"; 288218822Sdim }; 289218822Sdim 290218822Sdim i2c4: i2c@e6540000 { 291218822Sdim #address-cells = <1>; 292218822Sdim #size-cells = <0>; 293218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 294218822Sdim reg = <0 0xe6540000 0 0x428>; 295218822Sdim interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 296218822Sdim clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 297218822Sdim power-domains = <&pd_a3sp>; 298218822Sdim status = "disabled"; 299218822Sdim }; 300218822Sdim 301218822Sdim i2c6: i2c@e6550000 { 302218822Sdim #address-cells = <1>; 303218822Sdim #size-cells = <0>; 304218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 305218822Sdim reg = <0 0xe6550000 0 0x428>; 306218822Sdim interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 307218822Sdim clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 308218822Sdim power-domains = <&pd_a3sp>; 309218822Sdim status = "disabled"; 310218822Sdim }; 311218822Sdim 312218822Sdim i2c7: i2c@e6560000 { 313218822Sdim #address-cells = <1>; 314218822Sdim #size-cells = <0>; 315218822Sdim compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 316218822Sdim reg = <0 0xe6560000 0 0x428>; 317218822Sdim interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 318218822Sdim clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 319218822Sdim power-domains = <&pd_a3sp>; 320218822Sdim status = "disabled"; 321218822Sdim }; 322218822Sdim 32389857Sobrien i2c8: i2c@e6570000 { 32489857Sobrien #address-cells = <1>; 32589857Sobrien #size-cells = <0>; 32689857Sobrien compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 32789857Sobrien reg = <0 0xe6570000 0 0x428>; 32833965Sjdp interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 32989857Sobrien clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 33089857Sobrien power-domains = <&pd_a3sp>; 33189857Sobrien status = "disabled"; 332130561Sobrien }; 33360484Sobrien 33489857Sobrien scifb0: serial@e6c20000 { 33589857Sobrien compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 33633965Sjdp reg = <0 0xe6c20000 0 0x100>; 33789857Sobrien interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 33889857Sobrien clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 33933965Sjdp clock-names = "fck"; 340218822Sdim power-domains = <&pd_a3sp>; 341218822Sdim status = "disabled"; 342218822Sdim }; 34389857Sobrien 344218822Sdim scifb1: serial@e6c30000 { 34589857Sobrien compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 34689857Sobrien reg = <0 0xe6c30000 0 0x100>; 34789857Sobrien interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 34889857Sobrien clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 349218822Sdim clock-names = "fck"; 35089857Sobrien power-domains = <&pd_a3sp>; 35189857Sobrien status = "disabled"; 35289857Sobrien }; 35360484Sobrien 35460484Sobrien scifa0: serial@e6c40000 { 35533965Sjdp compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 356218822Sdim reg = <0 0xe6c40000 0 0x100>; 357218822Sdim interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 358218822Sdim clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 359218822Sdim clock-names = "fck"; 360218822Sdim power-domains = <&pd_a3sp>; 36133965Sjdp status = "disabled"; 362218822Sdim }; 363218822Sdim 364218822Sdim scifa1: serial@e6c50000 { 365218822Sdim compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 366104834Sobrien reg = <0 0xe6c50000 0 0x100>; 367104834Sobrien interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 368104834Sobrien clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 369218822Sdim clock-names = "fck"; 370104834Sobrien power-domains = <&pd_a3sp>; 371104834Sobrien status = "disabled"; 372104834Sobrien }; 373104834Sobrien 374104834Sobrien scifb2: serial@e6ce0000 { 375104834Sobrien compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 37633965Sjdp reg = <0 0xe6ce0000 0 0x100>; 37733965Sjdp interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 37833965Sjdp clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 379130561Sobrien clock-names = "fck"; 380130561Sobrien power-domains = <&pd_a3sp>; 381218822Sdim status = "disabled"; 382130561Sobrien }; 38333965Sjdp 38433965Sjdp scifb3: serial@e6cf0000 { 38560484Sobrien compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 38660484Sobrien reg = <0 0xe6cf0000 0 0x100>; 38760484Sobrien interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 38860484Sobrien clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 38977298Sobrien clock-names = "fck"; 39060484Sobrien power-domains = <&pd_c4>; 39160484Sobrien status = "disabled"; 39260484Sobrien }; 39360484Sobrien 39460484Sobrien sdhi0: mmc@ee100000 { 39560484Sobrien compatible = "renesas,sdhi-r8a73a4"; 39660484Sobrien reg = <0 0xee100000 0 0x100>; 39760484Sobrien interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 39860484Sobrien clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 39960484Sobrien power-domains = <&pd_a3sp>; 40033965Sjdp cap-sd-highspeed; 40160484Sobrien status = "disabled"; 40260484Sobrien }; 40333965Sjdp 40433965Sjdp sdhi1: mmc@ee120000 { 40533965Sjdp compatible = "renesas,sdhi-r8a73a4"; 40633965Sjdp reg = <0 0xee120000 0 0x100>; 40777298Sobrien interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 40833965Sjdp clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 40933965Sjdp power-domains = <&pd_a3sp>; 41033965Sjdp cap-sd-highspeed; 41133965Sjdp status = "disabled"; 41260484Sobrien }; 41333965Sjdp 41460484Sobrien sdhi2: mmc@ee140000 { 41533965Sjdp compatible = "renesas,sdhi-r8a73a4"; 41689857Sobrien reg = <0 0xee140000 0 0x100>; 41789857Sobrien interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 41833965Sjdp clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 41933965Sjdp power-domains = <&pd_a3sp>; 42033965Sjdp cap-sd-highspeed; 42133965Sjdp status = "disabled"; 42233965Sjdp }; 42333965Sjdp 42433965Sjdp mmcif0: mmc@ee200000 { 42533965Sjdp compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 42689857Sobrien reg = <0 0xee200000 0 0x80>; 42733965Sjdp interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 42889857Sobrien clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 42989857Sobrien power-domains = <&pd_a3sp>; 43089857Sobrien reg-io-width = <4>; 43189857Sobrien status = "disabled"; 43289857Sobrien }; 43389857Sobrien 43489857Sobrien mmcif1: mmc@ee220000 { 43589857Sobrien compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 43689857Sobrien reg = <0 0xee220000 0 0x80>; 43789857Sobrien interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 43889857Sobrien clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 43989857Sobrien power-domains = <&pd_a3sp>; 44089857Sobrien reg-io-width = <4>; 44189857Sobrien status = "disabled"; 44233965Sjdp }; 44333965Sjdp 44460484Sobrien gic: interrupt-controller@f1001000 { 44560484Sobrien compatible = "arm,gic-400"; 44660484Sobrien #interrupt-cells = <3>; 44777298Sobrien #address-cells = <0>; 44877298Sobrien interrupt-controller; 44977298Sobrien reg = <0 0xf1001000 0 0x1000>, 45089857Sobrien <0 0xf1002000 0 0x2000>, 45189857Sobrien <0 0xf1004000 0 0x2000>, 45289857Sobrien <0 0xf1006000 0 0x2000>; 45389857Sobrien interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 45433965Sjdp clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 45560484Sobrien clock-names = "clk"; 45660484Sobrien power-domains = <&pd_c4>; 45777298Sobrien }; 458218822Sdim 45933965Sjdp bsc: bus@fec10000 { 46060484Sobrien compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 46160484Sobrien "simple-pm-bus"; 46238889Sjdp #address-cells = <1>; 463130561Sobrien #size-cells = <1>; 46477298Sobrien ranges = <0 0 0 0x20000000>; 46577298Sobrien reg = <0 0xfec10000 0 0x400>; 46660484Sobrien clocks = <&zb_clk>; 46760484Sobrien power-domains = <&pd_c4>; 46833965Sjdp }; 46933965Sjdp 47033965Sjdp clocks { 47160484Sobrien #address-cells = <2>; 47260484Sobrien #size-cells = <2>; 47333965Sjdp ranges; 47489857Sobrien 47589857Sobrien /* External root clocks */ 47660484Sobrien extalr_clk: extalr { 477130561Sobrien compatible = "fixed-clock"; 478130561Sobrien #clock-cells = <0>; 47960484Sobrien /* This value must be overridden by the board. */ 480218822Sdim clock-frequency = <0>; 48160484Sobrien }; 48260484Sobrien extal1_clk: extal1 { 48389857Sobrien compatible = "fixed-clock"; 48489857Sobrien #clock-cells = <0>; 48589857Sobrien /* This value must be overridden by the board. */ 48660484Sobrien clock-frequency = <0>; 487218822Sdim }; 48860484Sobrien extal2_clk: extal2 { 48989857Sobrien compatible = "fixed-clock"; 49077298Sobrien #clock-cells = <0>; 49177298Sobrien /* This value must be overridden by the board. */ 49277298Sobrien clock-frequency = <0>; 493130561Sobrien }; 49460484Sobrien fsiack_clk: fsiack { 49560484Sobrien compatible = "fixed-clock"; 49689857Sobrien #clock-cells = <0>; 49789857Sobrien /* This value must be overridden by the board. */ 49860484Sobrien clock-frequency = <0>; 499218822Sdim }; 500218822Sdim fsibck_clk: fsibck { 501218822Sdim compatible = "fixed-clock"; 502218822Sdim #clock-cells = <0>; 50389857Sobrien /* This value must be overridden by the board. */ 50489857Sobrien clock-frequency = <0>; 50589857Sobrien }; 506130561Sobrien 50789857Sobrien /* Special CPG clocks */ 508130561Sobrien cpg_clocks: cpg_clocks@e6150000 { 509130561Sobrien compatible = "renesas,r8a73a4-cpg-clocks"; 510130561Sobrien reg = <0 0xe6150000 0 0x10000>; 511130561Sobrien clocks = <&extal1_clk>, <&extal2_clk>; 512130561Sobrien #clock-cells = <1>; 513130561Sobrien clock-output-names = "main", "pll0", "pll1", "pll2", 514130561Sobrien "pll2s", "pll2h", "z", "z2", 515130561Sobrien "i", "m3", "b", "m1", "m2", 516130561Sobrien "zx", "zs", "hp"; 517130561Sobrien }; 518130561Sobrien 519130561Sobrien /* Variable factor clocks (DIV6) */ 520218822Sdim zb_clk: zb_clk@e6150010 { 521218822Sdim compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 522130561Sobrien reg = <0 0xe6150010 0 4>; 523130561Sobrien clocks = <&pll1_div2_clk>, <0>, 524130561Sobrien <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 525130561Sobrien #clock-cells = <0>; 526130561Sobrien clock-output-names = "zb"; 527218822Sdim }; 528218822Sdim sdhi0_clk: sdhi0ck@e6150074 { 529130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 530130561Sobrien reg = <0 0xe6150074 0 4>; 531130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 532130561Sobrien <0>, <&extal2_clk>; 533130561Sobrien #clock-cells = <0>; 534130561Sobrien }; 535130561Sobrien sdhi1_clk: sdhi1ck@e6150078 { 536130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 537130561Sobrien reg = <0 0xe6150078 0 4>; 538130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 539130561Sobrien <0>, <&extal2_clk>; 540218822Sdim #clock-cells = <0>; 541218822Sdim }; 542130561Sobrien sdhi2_clk: sdhi2ck@e615007c { 543130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 544130561Sobrien reg = <0 0xe615007c 0 4>; 545130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 546130561Sobrien <0>, <&extal2_clk>; 547130561Sobrien #clock-cells = <0>; 548130561Sobrien }; 549130561Sobrien mmc0_clk: mmc0@e6150240 { 550130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 551130561Sobrien reg = <0 0xe6150240 0 4>; 552130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 553130561Sobrien <0>, <&extal2_clk>; 554130561Sobrien #clock-cells = <0>; 555130561Sobrien }; 556130561Sobrien mmc1_clk: mmc1@e6150244 { 557130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 558130561Sobrien reg = <0 0xe6150244 0 4>; 559130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 560130561Sobrien <0>, <&extal2_clk>; 561130561Sobrien #clock-cells = <0>; 562130561Sobrien }; 563130561Sobrien vclk1_clk: vclk1@e6150008 { 564130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 565130561Sobrien reg = <0 0xe6150008 0 4>; 566130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 567130561Sobrien <0>, <&extal2_clk>, <&main_div2_clk>, 568130561Sobrien <&extalr_clk>, <0>, <0>; 569130561Sobrien #clock-cells = <0>; 570130561Sobrien }; 571130561Sobrien vclk2_clk: vclk2@e615000c { 572130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 573130561Sobrien reg = <0 0xe615000c 0 4>; 574130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 575130561Sobrien <0>, <&extal2_clk>, <&main_div2_clk>, 576130561Sobrien <&extalr_clk>, <0>, <0>; 577130561Sobrien #clock-cells = <0>; 578130561Sobrien }; 579130561Sobrien vclk3_clk: vclk3@e615001c { 580130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 581130561Sobrien reg = <0 0xe615001c 0 4>; 582130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 583130561Sobrien <0>, <&extal2_clk>, <&main_div2_clk>, 584130561Sobrien <&extalr_clk>, <0>, <0>; 585130561Sobrien #clock-cells = <0>; 586130561Sobrien }; 587130561Sobrien vclk4_clk: vclk4@e6150014 { 588130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 589130561Sobrien reg = <0 0xe6150014 0 4>; 590130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 591130561Sobrien <0>, <&extal2_clk>, <&main_div2_clk>, 592130561Sobrien <&extalr_clk>, <0>, <0>; 593130561Sobrien #clock-cells = <0>; 594130561Sobrien }; 595130561Sobrien vclk5_clk: vclk5@e6150034 { 596130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 597130561Sobrien reg = <0 0xe6150034 0 4>; 598130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 599130561Sobrien <0>, <&extal2_clk>, <&main_div2_clk>, 600130561Sobrien <&extalr_clk>, <0>, <0>; 601130561Sobrien #clock-cells = <0>; 602130561Sobrien }; 603130561Sobrien fsia_clk: fsia@e6150018 { 604130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 60589857Sobrien reg = <0 0xe6150018 0 4>; 606130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 607130561Sobrien <&fsiack_clk>, <0>; 608130561Sobrien #clock-cells = <0>; 609130561Sobrien }; 610130561Sobrien fsib_clk: fsib@e6150090 { 611130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 612130561Sobrien reg = <0 0xe6150090 0 4>; 61389857Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 614130561Sobrien <&fsibck_clk>, <0>; 615130561Sobrien #clock-cells = <0>; 616130561Sobrien }; 617130561Sobrien mp_clk: mp@e6150080 { 618130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 619130561Sobrien reg = <0 0xe6150080 0 4>; 620130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 621130561Sobrien <&extal2_clk>, <&extal2_clk>; 622130561Sobrien #clock-cells = <0>; 623130561Sobrien }; 624130561Sobrien m4_clk: m4@e6150098 { 625130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 626130561Sobrien reg = <0 0xe6150098 0 4>; 627130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 628130561Sobrien #clock-cells = <0>; 629130561Sobrien }; 630130561Sobrien hsi_clk: hsi@e615026c { 631130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 632130561Sobrien reg = <0 0xe615026c 0 4>; 633130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 634218822Sdim <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 635218822Sdim #clock-cells = <0>; 636130561Sobrien }; 637130561Sobrien spuv_clk: spuv@e6150094 { 638130561Sobrien compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 639130561Sobrien reg = <0 0xe6150094 0 4>; 640130561Sobrien clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 641130561Sobrien <&extal2_clk>, <&extal2_clk>; 642130561Sobrien #clock-cells = <0>; 643130561Sobrien }; 644130561Sobrien 645130561Sobrien /* Fixed factor clocks */ 646130561Sobrien main_div2_clk: main_div2 { 647130561Sobrien compatible = "fixed-factor-clock"; 648130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 649130561Sobrien #clock-cells = <0>; 650130561Sobrien clock-div = <2>; 651130561Sobrien clock-mult = <1>; 652130561Sobrien }; 653130561Sobrien cp_clk: cp { 654218822Sdim compatible = "fixed-factor-clock"; 655218822Sdim clocks = <&main_div2_clk>; 656218822Sdim #clock-cells = <0>; 657218822Sdim clock-div = <1>; 658218822Sdim clock-mult = <1>; 659218822Sdim }; 660218822Sdim pll0_div2_clk: pll0_div2 { 661130561Sobrien compatible = "fixed-factor-clock"; 662130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 663130561Sobrien #clock-cells = <0>; 664130561Sobrien clock-div = <2>; 665130561Sobrien clock-mult = <1>; 666130561Sobrien }; 667130561Sobrien pll1_div2_clk: pll1_div2 { 668130561Sobrien compatible = "fixed-factor-clock"; 669130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 670130561Sobrien #clock-cells = <0>; 671130561Sobrien clock-div = <2>; 672130561Sobrien clock-mult = <1>; 673130561Sobrien }; 674130561Sobrien extal1_div2_clk: extal1_div2 { 675218822Sdim compatible = "fixed-factor-clock"; 676218822Sdim clocks = <&extal1_clk>; 677218822Sdim #clock-cells = <0>; 678218822Sdim clock-div = <2>; 679218822Sdim clock-mult = <1>; 680218822Sdim }; 681218822Sdim 682130561Sobrien /* Gate clocks */ 683130561Sobrien mstp1_clks: mstp1_clks@e6150134 { 684130561Sobrien compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 685130561Sobrien reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 686130561Sobrien clocks = <&cp_clk>, <&mp_clk>; 687130561Sobrien #clock-cells = <1>; 688218822Sdim clock-indices = < 689130561Sobrien R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3 690130561Sobrien >; 691130561Sobrien clock-output-names = 692130561Sobrien "tmu0", "tmu3"; 693130561Sobrien }; 694130561Sobrien mstp2_clks: mstp2_clks@e6150138 { 695130561Sobrien compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 696130561Sobrien reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 697130561Sobrien clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 698130561Sobrien <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 699130561Sobrien #clock-cells = <1>; 700130561Sobrien clock-indices = < 701130561Sobrien R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 702130561Sobrien R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 703130561Sobrien R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 704130561Sobrien R8A73A4_CLK_DMAC 705130561Sobrien >; 706130561Sobrien clock-output-names = 70789857Sobrien "scifa0", "scifa1", "scifb0", "scifb1", 708130561Sobrien "scifb2", "scifb3", "dmac"; 709130561Sobrien }; 710130561Sobrien mstp3_clks: mstp3_clks@e615013c { 711130561Sobrien compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 712130561Sobrien reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 713130561Sobrien clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 71489857Sobrien <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 715130561Sobrien <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 716130561Sobrien <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 717130561Sobrien R8A73A4_CLK_HP>, <&cpg_clocks 718130561Sobrien R8A73A4_CLK_HP>, <&extalr_clk>; 719130561Sobrien #clock-cells = <1>; 720218822Sdim clock-indices = < 721218822Sdim R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 722218822Sdim R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 723218822Sdim R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 724218822Sdim R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 725218822Sdim R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 726218822Sdim R8A73A4_CLK_CMT1 727130561Sobrien >; 728130561Sobrien clock-output-names = 729130561Sobrien "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 730130561Sobrien "mmcif0", "iic6", "iic7", "iic0", "iic1", 731130561Sobrien "cmt1"; 732130561Sobrien }; 733130561Sobrien mstp4_clks: mstp4_clks@e6150140 { 734218822Sdim compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 73589857Sobrien reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 736130561Sobrien clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, 737130561Sobrien <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 738130561Sobrien <&cpg_clocks R8A73A4_CLK_HP>; 739130561Sobrien #clock-cells = <1>; 740130561Sobrien clock-indices = < 741130561Sobrien R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS 742130561Sobrien R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 743130561Sobrien R8A73A4_CLK_IIC3 744130561Sobrien >; 745130561Sobrien clock-output-names = 746130561Sobrien "irqc", "intc-sys", "iic5", "iic4", "iic3"; 747130561Sobrien }; 748130561Sobrien mstp5_clks: mstp5_clks@e6150144 { 749130561Sobrien compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 750130561Sobrien reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 751130561Sobrien clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 752130561Sobrien #clock-cells = <1>; 753218822Sdim clock-indices = < 754218822Sdim R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 755218822Sdim >; 756130561Sobrien clock-output-names = 757130561Sobrien "thermal", "iic8"; 758130561Sobrien }; 759130561Sobrien }; 760130561Sobrien 761130561Sobrien prr: chipid@ff000044 { 762130561Sobrien compatible = "renesas,prr"; 763130561Sobrien reg = <0 0xff000044 0 4>; 764130561Sobrien }; 765130561Sobrien 766130561Sobrien sysc: system-controller@e6180000 { 767130561Sobrien compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 768130561Sobrien reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 769130561Sobrien 770130561Sobrien pm-domains { 771130561Sobrien pd_c5: c5 { 772130561Sobrien #address-cells = <1>; 773130561Sobrien #size-cells = <0>; 774130561Sobrien #power-domain-cells = <0>; 775130561Sobrien 776130561Sobrien pd_c4: c4@0 { 777130561Sobrien reg = <0>; 778130561Sobrien #address-cells = <1>; 779130561Sobrien #size-cells = <0>; 780130561Sobrien #power-domain-cells = <0>; 781130561Sobrien 782130561Sobrien pd_a3sg: a3sg@16 { 783130561Sobrien reg = <16>; 784130561Sobrien #power-domain-cells = <0>; 785130561Sobrien }; 786130561Sobrien 787130561Sobrien pd_a3ex: a3ex@17 { 788130561Sobrien reg = <17>; 789130561Sobrien #power-domain-cells = <0>; 790130561Sobrien }; 791130561Sobrien 792130561Sobrien pd_a3sp: a3sp@18 { 793130561Sobrien reg = <18>; 794130561Sobrien #address-cells = <1>; 795130561Sobrien #size-cells = <0>; 796130561Sobrien #power-domain-cells = <0>; 797130561Sobrien 798130561Sobrien pd_a2us: a2us@19 { 799130561Sobrien reg = <19>; 800130561Sobrien #power-domain-cells = <0>; 801130561Sobrien }; 802130561Sobrien }; 803130561Sobrien 804130561Sobrien pd_a3sm: a3sm@20 { 805130561Sobrien reg = <20>; 806130561Sobrien #address-cells = <1>; 807130561Sobrien #size-cells = <0>; 808130561Sobrien #power-domain-cells = <0>; 809130561Sobrien 810130561Sobrien pd_a2sl: a2sl@21 { 811130561Sobrien reg = <21>; 812130561Sobrien #power-domain-cells = <0>; 813130561Sobrien }; 814130561Sobrien }; 815130561Sobrien 816130561Sobrien pd_a3km: a3km@22 { 817130561Sobrien reg = <22>; 818130561Sobrien #address-cells = <1>; 819130561Sobrien #size-cells = <0>; 820130561Sobrien #power-domain-cells = <0>; 821130561Sobrien 822130561Sobrien pd_a2kl: a2kl@23 { 823130561Sobrien reg = <23>; 824130561Sobrien #power-domain-cells = <0>; 825130561Sobrien }; 826130561Sobrien }; 827130561Sobrien }; 828130561Sobrien 829130561Sobrien pd_c4ma: c4ma@1 { 830130561Sobrien reg = <1>; 831130561Sobrien #power-domain-cells = <0>; 832130561Sobrien }; 833130561Sobrien 834130561Sobrien pd_c4cl: c4cl@2 { 835130561Sobrien reg = <2>; 836130561Sobrien #power-domain-cells = <0>; 837130561Sobrien }; 838130561Sobrien 839130561Sobrien pd_d4: d4@3 { 840130561Sobrien reg = <3>; 841130561Sobrien #power-domain-cells = <0>; 842130561Sobrien }; 843130561Sobrien 844130561Sobrien pd_a4bc: a4bc@4 { 845130561Sobrien reg = <4>; 846130561Sobrien #address-cells = <1>; 847130561Sobrien #size-cells = <0>; 848130561Sobrien #power-domain-cells = <0>; 849130561Sobrien 850130561Sobrien pd_a3bc: a3bc@5 { 851130561Sobrien reg = <5>; 852130561Sobrien #power-domain-cells = <0>; 853130561Sobrien }; 854130561Sobrien }; 855130561Sobrien 856218822Sdim pd_a4l: a4l@6 { 857130561Sobrien reg = <6>; 858130561Sobrien #power-domain-cells = <0>; 859218822Sdim }; 860130561Sobrien 861218822Sdim pd_a4lc: a4lc@7 { 862130561Sobrien reg = <7>; 863218822Sdim #power-domain-cells = <0>; 864130561Sobrien }; 865130561Sobrien 866218822Sdim pd_a4mp: a4mp@8 { 867130561Sobrien reg = <8>; 868218822Sdim #address-cells = <1>; 869130561Sobrien #size-cells = <0>; 870130561Sobrien #power-domain-cells = <0>; 871130561Sobrien 87289857Sobrien pd_a3mp: a3mp@9 { 873130561Sobrien reg = <9>; 874130561Sobrien #power-domain-cells = <0>; 875130561Sobrien }; 876130561Sobrien 877130561Sobrien pd_a3vc: a3vc@10 { 878218822Sdim reg = <10>; 879218822Sdim #power-domain-cells = <0>; 880130561Sobrien }; 881218822Sdim }; 882130561Sobrien 883218822Sdim pd_a4sf: a4sf@11 { 884130561Sobrien reg = <11>; 885130561Sobrien #power-domain-cells = <0>; 886130561Sobrien }; 887130561Sobrien 888130561Sobrien pd_a3r: a3r@12 { 889130561Sobrien reg = <12>; 890130561Sobrien #address-cells = <1>; 891130561Sobrien #size-cells = <0>; 892130561Sobrien #power-domain-cells = <0>; 893130561Sobrien 894130561Sobrien pd_a2rv: a2rv@13 { 895130561Sobrien reg = <13>; 896130561Sobrien #power-domain-cells = <0>; 897130561Sobrien }; 898130561Sobrien 899218822Sdim pd_a2is: a2is@14 { 900218822Sdim reg = <14>; 901218822Sdim #power-domain-cells = <0>; 902218822Sdim }; 903218822Sdim }; 904218822Sdim }; 905218822Sdim }; 906130561Sobrien }; 907130561Sobrien}; 908130561Sobrien