155714Skris// SPDX-License-Identifier: GPL-2.0-only 255714Skris/* 355714Skris * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com> 455714Skris */ 555714Skris 655714Skris/dts-v1/; 755714Skris 8280304Sjkim#include <dt-bindings/gpio/gpio.h> 955714Skris#include <dt-bindings/input/input.h> 1055714Skris#include "imx6sx.dtsi" 1155714Skris 1255714Skris/ { 1355714Skris model = "Softing VIN|ING 2000"; 1455714Skris compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; 15280304Sjkim 1655714Skris chosen { 1755714Skris stdout-path = &uart1; 1855714Skris }; 1955714Skris 2055714Skris memory@80000000 { 2155714Skris device_type = "memory"; 22280304Sjkim reg = <0x80000000 0x40000000>; 2355714Skris }; 2455714Skris 2555714Skris reg_usb_otg1_vbus: regulator-usb_otg1_vbus { 2655714Skris compatible = "regulator-fixed"; 2755714Skris regulator-name = "usb_otg1_vbus"; 2855714Skris pinctrl-names = "default"; 2955714Skris pinctrl-0 = <&pinctrl_usb_otg1>; 3055714Skris regulator-min-microvolt = <5000000>; 3155714Skris regulator-max-microvolt = <5000000>; 3255714Skris gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 3355714Skris enable-active-high; 3455714Skris }; 3555714Skris 3655714Skris reg_peri_3v3: regulator-peri_3v3 { 37280304Sjkim compatible = "regulator-fixed"; 3855714Skris regulator-name = "peri_3v3"; 3955714Skris regulator-min-microvolt = <3300000>; 40280304Sjkim regulator-max-microvolt = <3300000>; 4155714Skris }; 4255714Skris 4355714Skris led-controller { 4455714Skris compatible = "pwm-leds"; 4555714Skris 4655714Skris led-1 { 4755714Skris label = "red"; 4855714Skris max-brightness = <255>; 4955714Skris pwms = <&pwm6 0 50000 0>; 5055714Skris }; 5155714Skris 52280304Sjkim led-2 { 5355714Skris label = "green"; 5455714Skris max-brightness = <255>; 5555714Skris pwms = <&pwm2 0 50000 0>; 5655714Skris }; 5755714Skris 5855714Skris led-3 { 5955714Skris label = "blue"; 6055714Skris max-brightness = <255>; 6155714Skris pwms = <&pwm1 0 50000 0>; 6255714Skris }; 6355714Skris }; 64109998Smarkm}; 6555714Skris 6655714Skris&adc1 { 6755714Skris vref-supply = <®_peri_3v3>; 6855714Skris status = "okay"; 69160814Ssimon}; 70280304Sjkim 71280304Sjkim&cpu0 { 72280304Sjkim /* 73280304Sjkim * This board has a shared rail of reg_arm and reg_soc (supplied by 74280304Sjkim * sw1a_reg) which is modeled below, but still this module behaves 75280304Sjkim * unstable without higher voltages. Hence, set higher voltages here. 76280304Sjkim */ 77280304Sjkim operating-points = < 7855714Skris /* kHz uV */ 7955714Skris 996000 1250000 80280304Sjkim 792000 1175000 81280304Sjkim 396000 1175000 82280304Sjkim 198000 1175000 83280304Sjkim >; 84280304Sjkim fsl,soc-operating-points = < 85280304Sjkim /* ARM kHz SOC uV */ 8655714Skris 996000 1250000 87280304Sjkim 792000 1175000 88280304Sjkim 396000 1175000 89280304Sjkim 198000 1175000 90280304Sjkim >; 91280304Sjkim}; 9255714Skris 93280304Sjkim&ecspi4 { 94280304Sjkim pinctrl-names = "default"; 95280304Sjkim pinctrl-0 = <&pinctrl_ecspi4>; 96238405Sjkim cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; 97280304Sjkim status = "okay"; 98280304Sjkim}; 99280304Sjkim 100280304Sjkim&fec1 { 101280304Sjkim pinctrl-names = "default"; 102280304Sjkim pinctrl-0 = <&pinctrl_enet1>; 103109998Smarkm phy-supply = <®_peri_3v3>; 104280304Sjkim phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 105280304Sjkim phy-reset-duration = <5>; 106280304Sjkim phy-mode = "rmii"; 107291721Sjkim phy-handle = <ðphy0>; 108291721Sjkim status = "okay"; 109280304Sjkim 110280304Sjkim mdio { 111280304Sjkim #address-cells = <1>; 112280304Sjkim #size-cells = <0>; 113280304Sjkim 114280304Sjkim ethphy0: ethernet0-phy@0 { 115280304Sjkim reg = <0>; 116280304Sjkim max-speed = <100>; 117280304Sjkim interrupt-parent = <&gpio2>; 118280304Sjkim interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 119280304Sjkim }; 12055714Skris }; 121280304Sjkim}; 122280304Sjkim 123280304Sjkim&fec2 { 124280304Sjkim pinctrl-names = "default"; 125280304Sjkim pinctrl-0 = <&pinctrl_enet2>; 126280304Sjkim phy-supply = <®_peri_3v3>; 127280304Sjkim phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 128280304Sjkim phy-reset-duration = <5>; 129280304Sjkim phy-mode = "rmii"; 130280304Sjkim phy-handle = <ðphy1>; 131280304Sjkim status = "okay"; 132280304Sjkim 133280304Sjkim mdio { 134280304Sjkim #address-cells = <1>; 13555714Skris #size-cells = <0>; 136280304Sjkim 137280304Sjkim ethphy1: ethernet1-phy@0 { 13855714Skris reg = <0>; 139280304Sjkim max-speed = <100>; 140280304Sjkim interrupt-parent = <&gpio2>; 141280304Sjkim interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 142291721Sjkim }; 143280304Sjkim }; 144280304Sjkim}; 145280304Sjkim 146280304Sjkim&flexcan1 { 147280304Sjkim pinctrl-names = "default"; 148280304Sjkim pinctrl-0 = <&pinctrl_flexcan1>; 149280304Sjkim status = "okay"; 150280304Sjkim}; 151280304Sjkim 152280304Sjkim&flexcan2 { 15355714Skris pinctrl-names = "default"; 154280304Sjkim pinctrl-0 = <&pinctrl_flexcan2>; 155280304Sjkim status = "okay"; 156280304Sjkim}; 157280304Sjkim 158280304Sjkim&i2c1 { 159280304Sjkim clock-frequency = <100000>; 160280304Sjkim pinctrl-names = "default"; 161280304Sjkim pinctrl-0 = <&pinctrl_i2c1>; 162280304Sjkim status = "okay"; 163280304Sjkim 164280304Sjkim proximity: sx9500@28 { 165280304Sjkim compatible = "semtech,sx9500"; 166280304Sjkim reg = <0x28>; 167280304Sjkim pinctrl-names = "default"; 168280304Sjkim pinctrl-0 = <&pinctrl_sx9500>; 169280304Sjkim interrupt-parent = <&gpio2>; 170280304Sjkim interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 171280304Sjkim reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 172280304Sjkim }; 173280304Sjkim 174280304Sjkim pmic: pmic@8 { 175280304Sjkim compatible = "fsl,pfuze200"; 176280304Sjkim reg = <0x08>; 177280304Sjkim 178280304Sjkim regulators { 179280304Sjkim sw1a_reg: sw1ab { 180280304Sjkim regulator-min-microvolt = <300000>; 181280304Sjkim regulator-max-microvolt = <1875000>; 182280304Sjkim regulator-boot-on; 183280304Sjkim regulator-always-on; 184280304Sjkim regulator-ramp-delay = <6250>; 185280304Sjkim }; 186280304Sjkim 187280304Sjkim sw2_reg: sw2 { 188280304Sjkim regulator-min-microvolt = <800000>; 189280304Sjkim regulator-max-microvolt = <3300000>; 190280304Sjkim regulator-boot-on; 191280304Sjkim regulator-always-on; 192280304Sjkim }; 193291721Sjkim 194280304Sjkim sw3a_reg: sw3a { 195280304Sjkim regulator-min-microvolt = <400000>; 196 regulator-max-microvolt = <1975000>; 197 regulator-boot-on; 198 regulator-always-on; 199 }; 200 201 sw3b_reg: sw3b { 202 regulator-min-microvolt = <400000>; 203 regulator-max-microvolt = <1975000>; 204 regulator-boot-on; 205 regulator-always-on; 206 }; 207 208 snvs_reg: vsnvs { 209 regulator-min-microvolt = <1000000>; 210 regulator-max-microvolt = <3000000>; 211 regulator-boot-on; 212 regulator-always-on; 213 }; 214 215 vref_reg: vrefddr { 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 220 vgen1_reg: vgen1 { 221 regulator-min-microvolt = <800000>; 222 regulator-max-microvolt = <1550000>; 223 regulator-always-on; 224 }; 225 226 vgen2_reg: vgen2 { 227 regulator-min-microvolt = <800000>; 228 regulator-max-microvolt = <1550000>; 229 }; 230 231 vgen3_reg: vgen3 { 232 regulator-min-microvolt = <1800000>; 233 regulator-max-microvolt = <3300000>; 234 regulator-always-on; 235 }; 236 237 vgen4_reg: vgen4 { 238 regulator-min-microvolt = <1800000>; 239 regulator-max-microvolt = <3300000>; 240 regulator-always-on; 241 }; 242 243 vgen5_reg: vgen5 { 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-always-on; 247 }; 248 249 vgen6_reg: vgen6 { 250 regulator-min-microvolt = <1800000>; 251 regulator-max-microvolt = <3300000>; 252 regulator-always-on; 253 }; 254 }; 255 }; 256}; 257 258&i2c3 { 259 clock-frequency = <100000>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_i2c3>; 262 status = "okay"; 263}; 264 265&iomuxc { 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_gpios>; 268 269 pinctrl_ecspi4: ecspi4grp { 270 fsl,pins = < 271 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 272 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 273 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 274 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 275 >; 276 }; 277 278 pinctrl_enet1: enet1grp { 279 fsl,pins = < 280 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 281 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 282 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 283 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 284 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 285 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 286 MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 287 /* LAN8720 PHY Reset */ 288 MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 289 /* MDIO */ 290 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 291 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 292 /* IRQ from PHY */ 293 MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 294 >; 295 }; 296 297 pinctrl_enet2: enet2grp { 298 fsl,pins = < 299 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 300 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 301 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 302 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 303 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 304 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 305 MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 306 /* LAN8720 PHY Reset */ 307 MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 308 /* MDIO */ 309 MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 310 MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 311 /* IRQ from PHY */ 312 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 313 >; 314 }; 315 316 pinctrl_flexcan1: flexcan1grp { 317 fsl,pins = < 318 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 319 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 320 >; 321 }; 322 323 pinctrl_flexcan2: flexcan2grp { 324 fsl,pins = < 325 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 326 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 327 >; 328 }; 329 330 pinctrl_gpios: gpiosgrp { 331 fsl,pins = < 332 /* reset external uC */ 333 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 334 /* IRQ from external uC */ 335 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 336 /* overcurrent detection */ 337 MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 338 >; 339 }; 340 341 pinctrl_i2c1: i2c1grp { 342 fsl,pins = < 343 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 344 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 345 >; 346 }; 347 348 pinctrl_i2c3: i2c3grp { 349 fsl,pins = < 350 MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 351 MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 352 >; 353 }; 354 355 pinctrl_pcie: pciegrp { 356 fsl,pins = < 357 MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 358 >; 359 }; 360 361 pinctrl_pwm1: pwm1grp-1 { 362 fsl,pins = < 363 /* blue LED */ 364 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 365 >; 366 }; 367 368 pinctrl_pwm2: pwm2grp-1 { 369 fsl,pins = < 370 /* green LED */ 371 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 372 >; 373 }; 374 375 pinctrl_pwm6: pwm6grp-1 { 376 fsl,pins = < 377 /* red LED */ 378 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 379 >; 380 }; 381 382 pinctrl_sx9500: sx9500grp { 383 fsl,pins = < 384 /* Reset */ 385 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 386 /* IRQ */ 387 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 388 >; 389 }; 390 391 pinctrl_uart1: uart1grp { 392 fsl,pins = < 393 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 394 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 395 >; 396 }; 397 398 pinctrl_uart2: uart2grp { 399 fsl,pins = < 400 MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 401 MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 402 >; 403 }; 404 405 pinctrl_usb_otg1: usbotg1grp { 406 fsl,pins = < 407 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 408 >; 409 }; 410 411 pinctrl_usb_otg1_id: usbotg1idgrp { 412 fsl,pins = < 413 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 414 >; 415 }; 416 417 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { 418 fsl,pins = < 419 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 420 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 421 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 422 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 423 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 424 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 425 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 426 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 427 >; 428 }; 429 430 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 431 fsl,pins = < 432 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 433 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 434 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 435 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 436 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 437 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 438 >; 439 }; 440 441 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 442 fsl,pins = < 443 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 444 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 445 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 446 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 447 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 448 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 449 >; 450 }; 451 452 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { 453 fsl,pins = < 454 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 455 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 456 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 457 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 458 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 459 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 460 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 461 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 462 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 463 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 464 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 465 >; 466 }; 467 468 pinctrl_usdhc4_100mhz: usdhc4-100mhz { 469 fsl,pins = < 470 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 471 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 472 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 473 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 474 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 475 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 476 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 477 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 478 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 479 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 480 >; 481 }; 482 483 pinctrl_usdhc4_200mhz: usdhc4-200mhz { 484 fsl,pins = < 485 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 486 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 487 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 488 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 489 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 490 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 491 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 492 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 493 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 494 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 495 >; 496 }; 497}; 498 499&pcie { 500 pinctrl-names = "default"; 501 pinctrl-0 = <&pinctrl_pcie>; 502 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; 503 reset-gpio-active-high; 504 status = "okay"; 505}; 506 507&pwm1 { 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_pwm1>; 510}; 511 512&pwm2 { 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pinctrl_pwm2>; 515}; 516 517&pwm6 { 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_pwm6>; 520}; 521 522®_arm { 523 vin-supply = <&sw1a_reg>; 524}; 525 526®_soc { 527 vin-supply = <&sw1a_reg>; 528}; 529 530&snvs_poweroff { 531 status = "okay"; 532}; 533 534&uart1 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_uart1>; 537 status = "okay"; 538}; 539 540&uart2 { 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pinctrl_uart2>; 543 status = "okay"; 544}; 545 546&usbotg1 { 547 vbus-supply = <®_usb_otg1_vbus>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pinctrl_usb_otg1_id>; 550 status = "okay"; 551}; 552 553&usbotg2 { 554 dr_mode = "host"; 555 status = "okay"; 556}; 557 558&usdhc2 { 559 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 560 pinctrl-0 = <&pinctrl_usdhc2_50mhz>; 561 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 562 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 563 cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; 564 keep-power-in-suspend; 565 status = "okay"; 566}; 567 568&usdhc4 { 569 /* hs200-mode is currently unsupported because Vccq is on 3.1V, but 570 * not on necessary 1.8V. 571 */ 572 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 573 pinctrl-0 = <&pinctrl_usdhc4_50mhz>; 574 pinctrl-1 = <&pinctrl_usdhc4_100mhz>; 575 pinctrl-2 = <&pinctrl_usdhc4_200mhz>; 576 bus-width = <8>; 577 keep-power-in-suspend; 578 non-removable; 579 cap-mmc-hw-reset; 580 status = "okay"; 581}; 582