1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/leds/common.h>
7
8/ {
9	chosen {
10		stdout-path = &uart2;
11	};
12
13	aliases {
14		can0 = &can1;
15		can1 = &can2;
16		ethernet0 = &fec;
17		ethernet1 = &lan1;
18		ethernet2 = &lan2;
19		mdio-gpio0 = &mdio;
20		nand = &gpmi;
21		rtc0 = &i2c_rtc;
22		rtc1 = &snvs;
23		switch0 = &switch;
24		usb0 = &usbh1;
25		usb1 = &usbotg;
26	};
27
28	iio-hwmon {
29		compatible = "iio-hwmon";
30		io-channels = <&adc 0>, /* 24V */
31		              <&adc 1>; /* temperature */
32	};
33
34	leds {
35		compatible = "gpio-leds";
36
37		led-0 {
38			label = "D1";
39			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
40			function = LED_FUNCTION_STATUS;
41			default-state = "on";
42			linux,default-trigger = "heartbeat";
43		};
44
45		led-1 {
46			label = "D2";
47			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
48			default-state = "off";
49		};
50
51		led-2 {
52			label = "D3";
53			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
54			default-state = "on";
55		};
56	};
57
58	mdio: mdio {
59		compatible = "microchip,mdio-smi0";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_mdio>;
62		#address-cells = <1>;
63		#size-cells = <0>;
64		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
65			<&gpio1 22 GPIO_ACTIVE_HIGH>;
66
67		switch: switch@0 {
68			compatible = "microchip,ksz8873";
69			pinctrl-names = "default";
70			pinctrl-0 = <&pinctrl_switch>;
71			interrupt-parent = <&gpio3>;
72			interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
73			reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
74			reg = <0>;
75
76			ports {
77				#address-cells = <1>;
78				#size-cells = <0>;
79
80				lan1: ports@0 {
81					reg = <0>;
82					phy-mode = "internal";
83					label = "lan1";
84				};
85
86				lan2: ports@1 {
87					reg = <1>;
88					phy-mode = "internal";
89					label = "lan2";
90				};
91
92				ports@2 {
93					reg = <2>;
94					label = "cpu";
95					ethernet = <&fec>;
96					phy-mode = "rmii";
97
98					fixed-link {
99						speed = <100>;
100						full-duplex;
101					};
102				};
103			};
104		};
105
106	};
107
108	clk50m_phy: phy-clock {
109		compatible = "fixed-clock";
110		#clock-cells = <0>;
111		clock-frequency = <50000000>;
112		clock-output-names = "enet_ref_pad";
113	};
114
115	reg_3v3: regulator-3v3 {
116		compatible = "regulator-fixed";
117		vin-supply = <&reg_5v0>;
118		regulator-name = "3v3";
119		regulator-min-microvolt = <3300000>;
120		regulator-max-microvolt = <3300000>;
121	};
122
123	reg_5v0: regulator-5v0 {
124		compatible = "regulator-fixed";
125		regulator-name = "5v0";
126		regulator-min-microvolt = <5000000>;
127		regulator-max-microvolt = <5000000>;
128	};
129
130	reg_24v0: regulator-24v0 {
131		compatible = "regulator-fixed";
132		regulator-name = "24v0";
133		regulator-min-microvolt = <24000000>;
134		regulator-max-microvolt = <24000000>;
135	};
136
137	reg_can1_stby: regulator-can1-stby {
138		compatible = "regulator-fixed";
139		pinctrl-names = "default";
140		pinctrl-0 = <&pinctrl_can1_stby>;
141		regulator-name = "can1-3v3";
142		regulator-min-microvolt = <3300000>;
143		regulator-max-microvolt = <3300000>;
144		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
145	};
146
147	reg_can2_stby: regulator-can2-stby {
148		compatible = "regulator-fixed";
149		pinctrl-names = "default";
150		pinctrl-0 = <&pinctrl_can2_stby>;
151		regulator-name = "can2-3v3";
152		regulator-min-microvolt = <3300000>;
153		regulator-max-microvolt = <3300000>;
154		gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
155	};
156
157	reg_tft_vcom: regulator-tft-vcom {
158		compatible = "pwm-regulator";
159		pwms = <&pwm3 0 20000 0>;
160		regulator-name = "tft_vcom";
161		regulator-min-microvolt = <3600000>;
162		regulator-max-microvolt = <3600000>;
163		regulator-always-on;
164		voltage-table = <3600000 26>;
165	};
166
167	reg_vcc_mmc: regulator-vcc-mmc {
168		compatible = "regulator-fixed";
169		pinctrl-names = "default";
170		pinctrl-0 = <&pinctrl_vcc_mmc>;
171		vin-supply = <&reg_3v3>;
172		regulator-name = "mmc_vcc_supply";
173		regulator-min-microvolt = <3300000>;
174		regulator-max-microvolt = <3300000>;
175		regulator-always-on;
176		regulator-boot-on;
177		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
178		enable-active-high;
179		startup-delay-us = <100>;
180	};
181
182	reg_vcc_mmc_io: regulator-vcc-mmc-io {
183		compatible = "regulator-gpio";
184		pinctrl-names = "default";
185		pinctrl-0 = <&pinctrl_vcc_mmc_io>;
186		vin-supply = <&reg_5v0>;
187		regulator-name = "mmc_io_supply";
188		regulator-type = "voltage";
189		regulator-min-microvolt = <1800000>;
190		regulator-max-microvolt = <3300000>;
191		gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
192		enable-active-high;
193		states = <1800000 0x1>, <3300000 0x0>;
194		startup-delay-us = <100>;
195	};
196};
197
198&can1 {
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_can1>;
201	xceiver-supply = <&reg_can1_stby>;
202	status = "okay";
203};
204
205&can2 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_can2>;
208	xceiver-supply = <&reg_can2_stby>;
209	status = "okay";
210};
211
212&ecspi1 {
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_ecspi1>;
215	cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
216	status = "okay";
217
218	flash@0 {
219		compatible = "jedec,spi-nor";
220		spi-max-frequency = <54000000>;
221		reg = <0>;
222	};
223};
224
225&ecspi2 {
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_ecspi2>;
228	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
229	status = "okay";
230
231	adc: adc@0 {
232		compatible = "microchip,mcp3002";
233		reg = <0>;
234		vref-supply = <&reg_3v3>;
235		spi-max-frequency = <1000000>;
236		#io-channel-cells = <1>;
237	};
238};
239
240&clks {
241	clocks = <&clk50m_phy>;
242	clock-names = "enet_ref_pad";
243	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
244	assigned-clock-parents = <&clk50m_phy>;
245};
246
247&fec {
248	pinctrl-names = "default";
249	pinctrl-0 = <&pinctrl_enet>;
250	phy-mode = "rmii";
251	phy-supply = <&reg_3v3>;
252	status = "okay";
253
254	fixed-link {
255		speed = <100>;
256		full-duplex;
257	};
258};
259
260&gpmi {
261	pinctrl-names = "default";
262	pinctrl-0 = <&pinctrl_gpmi_nand>;
263	nand-on-flash-bbt;
264	#address-cells = <1>;
265	#size-cells = <0>;
266	status = "okay";
267};
268
269&i2c3 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_i2c3>;
272	clock-frequency = <400000>;
273	status = "okay";
274
275	i2c_rtc: rtc@51 {
276		compatible = "nxp,pcf85063";
277		reg = <0x51>;
278		quartz-load-femtofarads = <12500>;
279	};
280};
281
282&pwm2 {
283	pinctrl-names = "default";
284	pinctrl-0 = <&pinctrl_pwm2>;
285	status = "okay";
286};
287
288&pwm3 {
289	/* used for LCD contrast control */
290	pinctrl-names = "default";
291	pinctrl-0 = <&pinctrl_pwm3>;
292	status = "okay";
293};
294
295&uart2 {
296	pinctrl-names = "default";
297	pinctrl-0 = <&pinctrl_uart2>;
298	status = "okay";
299};
300
301&usbh1 {
302	vbus-supply = <&reg_5v0>;
303	disable-over-current;
304	status = "okay";
305};
306
307/* no usbh2 */
308&usbphynop1 {
309	status = "disabled";
310};
311
312/* no usbh3 */
313&usbphynop2 {
314	status = "disabled";
315};
316
317&usbotg {
318	vbus-supply = <&reg_5v0>;
319	disable-over-current;
320	status = "okay";
321};
322
323&usdhc3 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_usdhc3>;
326	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
327	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
328	cap-power-off-card;
329	full-pwr-cycle;
330	bus-width = <4>;
331	max-frequency = <50000000>;
332	cap-sd-highspeed;
333	sd-uhs-sdr12;
334	sd-uhs-sdr25;
335	sd-uhs-sdr50;
336	sd-uhs-ddr50;
337	mmc-ddr-1_8v;
338	vmmc-supply = <&reg_vcc_mmc>;
339	vqmmc-supply = <&reg_vcc_mmc_io>;
340	status = "okay";
341};
342
343&iomuxc {
344	pinctrl_can1: can1grp {
345		fsl,pins = <
346			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX			0x3008
347			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX			0x1b000
348		>;
349	};
350
351	pinctrl_can1_stby: can1stbygrp {
352		fsl,pins = <
353			MX6QDL_PAD_EIM_D31__GPIO3_IO31			0x13008
354		>;
355	};
356
357	pinctrl_can2: can2grp {
358		fsl,pins = <
359			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX		0x3008
360			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX		0x1b000
361		>;
362	};
363
364	pinctrl_can2_stby: can2stbygrp {
365		fsl,pins = <
366			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11			0x13008
367		>;
368	};
369
370	pinctrl_ecspi1: ecspi1grp {
371		fsl,pins = <
372			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x100b1
373			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0xb1
374			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0xb1
375			/* *no* external pull up */
376			MX6QDL_PAD_EIM_D24__GPIO3_IO24			0x58
377		>;
378	};
379
380	pinctrl_ecspi2: ecspi2grp {
381		fsl,pins = <
382			MX6QDL_PAD_EIM_OE__ECSPI2_MISO			0x100b1
383			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI			0xb1
384			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK			0xb1
385			/* external pull up */
386			MX6QDL_PAD_EIM_RW__GPIO2_IO26			0x58
387		>;
388	};
389
390	pinctrl_enet: enetgrp {
391		fsl,pins = <
392			/* RMII 50 MHz */
393			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x100f5
394			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x100f5
395			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x100c0
396			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x100c0
397			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x100f5
398			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x100f5
399			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0
400			MX6QDL_PAD_GPIO_5__GPIO1_IO05			0x58
401			/* GPIO for "link active" */
402			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24		0x3038
403		>;
404	};
405
406	pinctrl_gpmi_nand: gpminandgrp {
407		fsl,pins = <
408			MX6QDL_PAD_NANDF_CLE__NAND_CLE			0xb0b1
409			MX6QDL_PAD_NANDF_ALE__NAND_ALE			0xb0b1
410			MX6QDL_PAD_NANDF_RB0__NAND_READY_B		0xb000
411			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B		0xb0b1
412			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B		0xb0b1
413			MX6QDL_PAD_SD4_CMD__NAND_RE_B			0xb0b1
414			MX6QDL_PAD_SD4_CLK__NAND_WE_B			0xb0b1
415			MX6QDL_PAD_NANDF_D0__NAND_DATA00		0xb0b1
416			MX6QDL_PAD_NANDF_D1__NAND_DATA01		0xb0b1
417			MX6QDL_PAD_NANDF_D2__NAND_DATA02		0xb0b1
418			MX6QDL_PAD_NANDF_D3__NAND_DATA03		0xb0b1
419			MX6QDL_PAD_NANDF_D4__NAND_DATA04		0xb0b1
420			MX6QDL_PAD_NANDF_D5__NAND_DATA05		0xb0b1
421			MX6QDL_PAD_NANDF_D6__NAND_DATA06		0xb0b1
422			MX6QDL_PAD_NANDF_D7__NAND_DATA07		0xb0b1
423		>;
424	};
425
426	pinctrl_i2c3: i2c3grp {
427		fsl,pins = <
428			/* external 10 k pull up */
429			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x40010878
430			/* external 10 k pull up */
431			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x40010878
432		>;
433	};
434
435	pinctrl_mdio: mdiogrp {
436		fsl,pins = <
437			MX6QDL_PAD_ENET_MDIO__GPIO1_IO22		0x100b1
438			MX6QDL_PAD_ENET_MDC__GPIO1_IO31			0xb1
439		>;
440	};
441
442	pinctrl_pwm2: pwm2grp {
443		fsl,pins = <
444			MX6QDL_PAD_GPIO_1__PWM2_OUT			0x58
445		>;
446	};
447
448	pinctrl_pwm3: pwm3grp {
449		fsl,pins = <
450			MX6QDL_PAD_SD1_DAT1__PWM3_OUT			0x58
451		>;
452	};
453
454	pinctrl_switch: switchgrp {
455		fsl,pins = <
456			MX6QDL_PAD_EIM_D30__GPIO3_IO30			0xb0
457		>;
458	};
459
460	pinctrl_uart2: uart2grp {
461		fsl,pins = <
462			MX6QDL_PAD_EIM_D26__UART2_TX_DATA		0x1b0b1
463			MX6QDL_PAD_EIM_D27__UART2_RX_DATA		0x1b0b1
464		>;
465	};
466
467	pinctrl_usdhc3: usdhc3grp {
468		fsl,pins = <
469			/* SoC internal pull up required */
470			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17059
471			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10059
472			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17059
473			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17059
474			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17059
475			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17059
476			/* SoC internal pull up required */
477			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01			0x1b040
478			/* SoC internal pull up required */
479			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00			0x1b040
480		>;
481	};
482
483	pinctrl_vcc_mmc: vccmmcgrp {
484		fsl,pins = <
485			MX6QDL_PAD_SD3_RST__GPIO7_IO08			0x58
486		>;
487	};
488
489	pinctrl_vcc_mmc_io: vccmmciogrp {
490		fsl,pins = <
491			MX6QDL_PAD_GPIO_18__GPIO7_IO13			0x58
492		>;
493	};
494};
495