1/*
2 * Copyright 2015 Savoir-faire Linux
3 *
4 * This device tree is based on imx51-babbage.dts
5 *
6 * Licensed under the X11 license or the GPL v2 (or later)
7 */
8
9/dts-v1/;
10#include "imx51.dtsi"
11
12/ {
13	model = "Technologic Systems TS-4800";
14	compatible = "technologic,imx51-ts4800", "fsl,imx51";
15
16	chosen {
17		stdout-path = &uart1;
18	};
19
20	memory@90000000 {
21		device_type = "memory";
22		reg = <0x90000000 0x10000000>;
23	};
24
25	clocks {
26		ckih1 {
27			clock-frequency = <22579200>;
28		};
29
30		ckih2 {
31			clock-frequency = <24576000>;
32		};
33	};
34
35	backlight_reg: regulator-backlight {
36		compatible = "regulator-fixed";
37		pinctrl-names = "default";
38		pinctrl-0 = <&pinctrl_enable_lcd>;
39		regulator-name = "enable_lcd_reg";
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
43		enable-active-high;
44	};
45
46	backlight: backlight {
47		compatible = "pwm-backlight";
48		pwms = <&pwm1 0 78770>;
49		brightness-levels = <0 150 200 255>;
50		default-brightness-level = <1>;
51		power-supply = <&backlight_reg>;
52	};
53
54	display1: disp1 {
55		compatible = "fsl,imx-parallel-display";
56		interface-pix-fmt = "rgb24";
57		pinctrl-names = "default";
58		pinctrl-0 = <&pinctrl_lcd>;
59
60		display-timings {
61			800x480p60 {
62				native-mode;
63				clock-frequency = <30066000>;
64				hactive = <800>;
65				vactive = <480>;
66				hfront-porch = <50>;
67				hback-porch = <70>;
68				hsync-len = <50>;
69				vback-porch = <0>;
70				vfront-porch = <0>;
71				vsync-len = <50>;
72			};
73		};
74
75		port {
76			display0_in: endpoint {
77				remote-endpoint = <&ipu_di0_disp1>;
78			};
79		};
80	};
81};
82
83&esdhc1 {
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_esdhc1>;
86	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
87	wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
88	status = "okay";
89};
90
91&fec {
92	pinctrl-names = "default";
93	pinctrl-0 = <&pinctrl_fec>;
94	phy-mode = "mii";
95	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
96	phy-reset-duration = <1>;
97	status = "okay";
98};
99
100&i2c2 {
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_i2c2>;
103	status = "okay";
104
105	rtc: rtc@68 {
106		compatible = "st,m41t00";
107		reg = <0x68>;
108	};
109};
110
111&ipu_di0_disp1 {
112	remote-endpoint = <&display0_in>;
113};
114
115&pwm1 {
116	#pwm-cells = <2>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pinctrl_pwm_backlight>;
119	status = "okay";
120};
121
122&uart1 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&pinctrl_uart1>;
125	status = "okay";
126};
127
128&uart2 {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_uart2>;
131	status = "okay";
132};
133
134&uart3 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_uart3>;
137	status = "okay";
138};
139
140&weim {
141	pinctrl-names = "default";
142	pinctrl-0 = <&pinctrl_weim>;
143	status = "okay";
144
145	fpga@0 {
146		compatible = "simple-bus";
147		fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
148				      0x00000000 0x1c092480 0x00000000>;
149		reg = <0 0x0000000 0x1d000>;
150		#address-cells = <1>;
151		#size-cells = <1>;
152		ranges = <0 0 0 0x1d000>;
153
154		syscon: syscon@10000 {
155			compatible = "syscon", "simple-mfd";
156			reg = <0x10000 0x3d>;
157			reg-io-width = <2>;
158
159			wdt {
160				compatible = "technologic,ts4800-wdt";
161				syscon = <&syscon 0xe>;
162			};
163		};
164
165		touchscreen@12000 {
166			compatible = "technologic,ts4800-ts";
167			reg = <0x12000 0x1000>;
168			syscon = <&syscon 0x10 6>;
169		};
170
171		fpga_irqc: fpga-irqc@15000 {
172			compatible = "technologic,ts4800-irqc";
173			reg = <0x15000 0x1000>;
174			pinctrl-names = "default";
175			pinctrl-0 = <&pinctrl_interrupt_fpga>;
176			interrupt-parent = <&gpio2>;
177			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
178			interrupt-controller;
179			#interrupt-cells = <1>;
180		};
181
182		can@1a000 {
183			compatible = "technologic,sja1000";
184			reg = <0x1a000 0x100>;
185			interrupt-parent = <&fpga_irqc>;
186			interrupts = <1>;
187			reg-io-width = <2>;
188			nxp,tx-output-config = <0x06>;
189			nxp,external-clock-frequency = <24000000>;
190		};
191	};
192};
193
194&iomuxc {
195	pinctrl_ecspi1: ecspi1grp {
196		fsl,pins = <
197			MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
198			MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
199			MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
200			MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
201		>;
202	};
203
204	pinctrl_enable_lcd: enablelcdgrp {
205		fsl,pins = <
206			MX51_PAD_CSI2_D12__GPIO4_9		0x1c5
207		>;
208	};
209
210	pinctrl_esdhc1: esdhc1grp {
211		fsl,pins = <
212			MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
213			MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
214			MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
215			MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
216			MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
217			MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
218			MX51_PAD_GPIO1_0__GPIO1_0		0x100
219			MX51_PAD_GPIO1_1__GPIO1_1		0x100
220		>;
221	};
222
223	pinctrl_fec: fecgrp {
224		fsl,pins = <
225			MX51_PAD_EIM_EB2__FEC_MDIO		0x000001f5
226			MX51_PAD_EIM_EB3__FEC_RDATA1		0x00000085
227			MX51_PAD_EIM_CS2__FEC_RDATA2		0x00000085
228			MX51_PAD_EIM_CS3__FEC_RDATA3		0x00000085
229			MX51_PAD_EIM_CS4__FEC_RX_ER		0x00000180
230			MX51_PAD_EIM_CS5__FEC_CRS		0x00000180
231			MX51_PAD_DISP2_DAT10__FEC_COL		0x00000180
232			MX51_PAD_DISP2_DAT11__FEC_RX_CLK	0x00000180
233			MX51_PAD_DISP2_DAT14__FEC_RDATA0	0x00002180
234			MX51_PAD_DISP2_DAT15__FEC_TDATA0	0x00002004
235			MX51_PAD_NANDF_CS2__FEC_TX_ER		0x00002004
236			MX51_PAD_DI2_PIN2__FEC_MDC		0x00002004
237			MX51_PAD_DISP2_DAT6__FEC_TDATA1		0x00002004
238			MX51_PAD_DISP2_DAT7__FEC_TDATA2		0x00002004
239			MX51_PAD_DISP2_DAT8__FEC_TDATA3		0x00002004
240			MX51_PAD_DISP2_DAT9__FEC_TX_EN		0x00002004
241			MX51_PAD_DISP2_DAT13__FEC_TX_CLK	0x00002180
242			MX51_PAD_DISP2_DAT12__FEC_RX_DV		0x000020a4
243			MX51_PAD_EIM_A20__GPIO2_14		0x00000085 /* Phy Reset */
244		>;
245	};
246
247	pinctrl_i2c2: i2c2grp {
248		fsl,pins = <
249			MX51_PAD_KEY_COL4__I2C2_SCL		0x400001ed
250			MX51_PAD_KEY_COL5__I2C2_SDA		0x400001ed
251		>;
252	};
253
254	pinctrl_interrupt_fpga: fpgaicgrp {
255		fsl,pins = <
256			MX51_PAD_EIM_D27__GPIO2_9		0xe5
257		>;
258	};
259
260	pinctrl_lcd: lcdgrp {
261		fsl,pins = <
262			MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
263			MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
264			MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
265			MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
266			MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
267			MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
268			MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
269			MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
270			MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
271			MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
272			MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
273			MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
274			MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
275			MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
276			MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
277			MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
278			MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
279			MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
280			MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
281			MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
282			MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
283			MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
284			MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
285			MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
286			MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
287			MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
288			MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	0x5
289			MX51_PAD_DI_GP4__DI2_PIN15		0x5
290		>;
291	};
292
293	pinctrl_pwm_backlight: backlightgrp {
294		fsl,pins = <
295			MX51_PAD_GPIO1_2__PWM1_PWMO		0x80000000
296		>;
297	};
298
299	pinctrl_uart1: uart1grp {
300		fsl,pins = <
301			MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
302			MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
303		>;
304	};
305
306	pinctrl_uart2: uart2grp {
307		fsl,pins = <
308			MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
309			MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
310		>;
311	};
312
313	pinctrl_uart3: uart3grp {
314		fsl,pins = <
315			MX51_PAD_EIM_D25__UART3_RXD		0x1c5
316			MX51_PAD_EIM_D26__UART3_TXD		0x1c5
317		>;
318	};
319
320	pinctrl_weim: weimgrp {
321		fsl,pins = <
322			MX51_PAD_EIM_DTACK__EIM_DTACK		0x85
323			MX51_PAD_EIM_CS0__EIM_CS0		0x0
324			MX51_PAD_EIM_CS1__EIM_CS1		0x0
325			MX51_PAD_EIM_EB0__EIM_EB0		0x85
326			MX51_PAD_EIM_EB1__EIM_EB1		0x85
327			MX51_PAD_EIM_OE__EIM_OE			0x85
328			MX51_PAD_EIM_LBA__EIM_LBA		0x85
329		>;
330	};
331};
332