1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clock/at91.h> 16#include <dt-bindings/dma/at91.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/mfd/at91-usart.h> 19#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 model = "Microchip SAMA7G5 family SoC"; 24 compatible = "microchip,sama7g5"; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 interrupt-parent = <&gic>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0x0>; 37 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 38 clock-names = "cpu"; 39 operating-points-v2 = <&cpu_opp_table>; 40 #cooling-cells = <2>; /* min followed by max */ 41 }; 42 }; 43 44 cpu_opp_table: opp-table { 45 compatible = "operating-points-v2"; 46 47 opp-90000000 { 48 opp-hz = /bits/ 64 <90000000>; 49 opp-microvolt = <1050000 1050000 1225000>; 50 clock-latency-ns = <320000>; 51 }; 52 53 opp-250000000 { 54 opp-hz = /bits/ 64 <250000000>; 55 opp-microvolt = <1050000 1050000 1225000>; 56 clock-latency-ns = <320000>; 57 }; 58 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1050000 1050000 1225000>; 62 clock-latency-ns = <320000>; 63 opp-suspend; 64 }; 65 66 opp-800000000 { 67 opp-hz = /bits/ 64 <800000000>; 68 opp-microvolt = <1150000 1125000 1225000>; 69 clock-latency-ns = <320000>; 70 }; 71 72 opp-1000000002 { 73 opp-hz = /bits/ 64 <1000000002>; 74 opp-microvolt = <1250000 1225000 1300000>; 75 clock-latency-ns = <320000>; 76 }; 77 }; 78 79 thermal-zones { 80 cpu_thermal: cpu-thermal { 81 polling-delay-passive = <1000>; 82 polling-delay = <5000>; 83 thermal-sensors = <&thermal_sensor>; 84 85 trips { 86 cpu_normal: cpu-alert0 { 87 temperature = <90000>; 88 hysteresis = <0>; 89 type = "passive"; 90 }; 91 92 cpu_hot: cpu-alert1 { 93 temperature = <95000>; 94 hysteresis = <0>; 95 type = "passive"; 96 }; 97 98 cpu_critical: cpu-critical { 99 temperature = <100000>; 100 hysteresis = <0>; 101 type = "critical"; 102 }; 103 }; 104 105 cooling-maps { 106 map0 { 107 trip = <&cpu_normal>; 108 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 109 }; 110 111 map1 { 112 trip = <&cpu_hot>; 113 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 114 }; 115 }; 116 }; 117 }; 118 119 clocks { 120 slow_xtal: slow_xtal { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 }; 124 125 main_xtal: main_xtal { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 }; 129 130 usb_clk: usb_clk { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 clock-frequency = <48000000>; 134 }; 135 }; 136 137 vddout25: fixed-regulator-vddout25 { 138 compatible = "regulator-fixed"; 139 140 regulator-name = "VDDOUT25"; 141 regulator-min-microvolt = <2500000>; 142 regulator-max-microvolt = <2500000>; 143 regulator-boot-on; 144 status = "disabled"; 145 }; 146 147 ns_sram: sram@100000 { 148 compatible = "mmio-sram"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 reg = <0x100000 0x20000>; 152 ranges; 153 }; 154 155 thermal_sensor: thermal-sensor { 156 compatible = "generic-adc-thermal"; 157 #thermal-sensor-cells = <0>; 158 io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; 159 io-channel-names = "sensor-channel"; 160 }; 161 162 soc { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges; 167 168 nfc_sram: sram@600000 { 169 compatible = "mmio-sram"; 170 no-memory-wc; 171 reg = <0x00600000 0x2400>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges = <0 0x00600000 0x2400>; 175 }; 176 177 nfc_io: nfc-io@10000000 { 178 compatible = "atmel,sama5d3-nfc-io", "syscon"; 179 reg = <0x10000000 0x8000000>; 180 }; 181 182 ebi: ebi@40000000 { 183 compatible = "atmel,sama5d3-ebi"; 184 #address-cells = <2>; 185 #size-cells = <1>; 186 atmel,smc = <&hsmc>; 187 reg = <0x40000000 0x20000000>; 188 ranges = <0x0 0x0 0x40000000 0x8000000 189 0x1 0x0 0x48000000 0x8000000 190 0x2 0x0 0x50000000 0x8000000 191 0x3 0x0 0x58000000 0x8000000>; 192 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 193 status = "disabled"; 194 195 nand_controller: nand-controller { 196 compatible = "atmel,sama5d3-nand-controller"; 197 atmel,nfc-sram = <&nfc_sram>; 198 atmel,nfc-io = <&nfc_io>; 199 ecc-engine = <&pmecc>; 200 #address-cells = <2>; 201 #size-cells = <1>; 202 ranges; 203 status = "disabled"; 204 }; 205 }; 206 207 securam: sram@e0000000 { 208 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 209 reg = <0xe0000000 0x4000>; 210 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges = <0 0xe0000000 0x4000>; 214 no-memory-wc; 215 }; 216 217 secumod: secumod@e0004000 { 218 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 219 reg = <0xe0004000 0x4000>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 }; 223 224 sfrbu: sfr@e0008000 { 225 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 226 reg = <0xe0008000 0x20>; 227 }; 228 229 pioA: pinctrl@e0014000 { 230 compatible = "microchip,sama7g5-pinctrl"; 231 reg = <0xe0014000 0x800>; 232 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 242 }; 243 244 pmc: clock-controller@e0018000 { 245 compatible = "microchip,sama7g5-pmc", "syscon"; 246 reg = <0xe0018000 0x200>; 247 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 248 #clock-cells = <2>; 249 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 250 clock-names = "td_slck", "md_slck", "main_xtal"; 251 }; 252 253 reset_controller: reset-controller@e001d000 { 254 compatible = "microchip,sama7g5-rstc"; 255 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 256 #reset-cells = <1>; 257 clocks = <&clk32k 0>; 258 }; 259 260 shdwc: poweroff@e001d010 { 261 compatible = "microchip,sama7g5-shdwc", "syscon"; 262 reg = <0xe001d010 0x10>; 263 clocks = <&clk32k 0>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 atmel,wakeup-rtc-timer; 267 atmel,wakeup-rtt-timer; 268 status = "disabled"; 269 }; 270 271 rtt: rtc@e001d020 { 272 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 273 reg = <0xe001d020 0x30>; 274 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clk32k 0>; 276 }; 277 278 clk32k: clock-controller@e001d050 { 279 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 280 reg = <0xe001d050 0x4>; 281 clocks = <&slow_xtal>; 282 #clock-cells = <1>; 283 }; 284 285 gpbr: gpbr@e001d060 { 286 compatible = "microchip,sama7g5-gpbr", "syscon"; 287 reg = <0xe001d060 0x48>; 288 }; 289 290 rtc: rtc@e001d0a8 { 291 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 292 reg = <0xe001d0a8 0x30>; 293 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clk32k 1>; 295 }; 296 297 ps_wdt: watchdog@e001d180 { 298 compatible = "microchip,sama7g5-wdt"; 299 reg = <0xe001d180 0x24>; 300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clk32k 0>; 302 }; 303 304 chipid@e0020000 { 305 compatible = "microchip,sama7g5-chipid"; 306 reg = <0xe0020000 0x8>; 307 }; 308 309 tcb1: timer@e0800000 { 310 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0xe0800000 0x100>; 314 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 316 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 317 }; 318 319 hsmc: hsmc@e0808000 { 320 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 321 reg = <0xe0808000 0x1000>; 322 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges; 327 328 pmecc: ecc-engine@e0808070 { 329 compatible = "atmel,sama5d2-pmecc"; 330 reg = <0xe0808070 0x490>, 331 <0xe0808500 0x200>; 332 }; 333 }; 334 335 qspi0: spi@e080c000 { 336 compatible = "microchip,sama7g5-ospi"; 337 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 338 reg-names = "qspi_base", "qspi_mmap"; 339 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 340 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 341 <&dma0 AT91_XDMAC_DT_PERID(40)>; 342 dma-names = "tx", "rx"; 343 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 344 clock-names = "pclk", "gclk"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 }; 349 350 qspi1: spi@e0810000 { 351 compatible = "microchip,sama7g5-qspi"; 352 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 353 reg-names = "qspi_base", "qspi_mmap"; 354 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 355 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 356 <&dma0 AT91_XDMAC_DT_PERID(42)>; 357 dma-names = "tx", "rx"; 358 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 359 clock-names = "pclk", "gclk"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 can0: can@e0828000 { 366 compatible = "bosch,m_can"; 367 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 368 reg-names = "m_can", "message_ram"; 369 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "int0", "int1"; 372 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 373 clock-names = "hclk", "cclk"; 374 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 375 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 376 assigned-clock-rates = <40000000>; 377 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 378 status = "disabled"; 379 }; 380 381 can1: can@e082c000 { 382 compatible = "bosch,m_can"; 383 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 384 reg-names = "m_can", "message_ram"; 385 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "int0", "int1"; 388 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 389 clock-names = "hclk", "cclk"; 390 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 391 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 392 assigned-clock-rates = <40000000>; 393 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 394 status = "disabled"; 395 }; 396 397 can2: can@e0830000 { 398 compatible = "bosch,m_can"; 399 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 400 reg-names = "m_can", "message_ram"; 401 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "int0", "int1"; 404 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 405 clock-names = "hclk", "cclk"; 406 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 407 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 408 assigned-clock-rates = <40000000>; 409 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 410 status = "disabled"; 411 }; 412 413 can3: can@e0834000 { 414 compatible = "bosch,m_can"; 415 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 416 reg-names = "m_can", "message_ram"; 417 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 419 interrupt-names = "int0", "int1"; 420 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 421 clock-names = "hclk", "cclk"; 422 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 423 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 424 assigned-clock-rates = <40000000>; 425 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 426 status = "disabled"; 427 }; 428 429 can4: can@e0838000 { 430 compatible = "bosch,m_can"; 431 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 432 reg-names = "m_can", "message_ram"; 433 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "int0", "int1"; 436 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 437 clock-names = "hclk", "cclk"; 438 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 439 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 440 assigned-clock-rates = <40000000>; 441 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 442 status = "disabled"; 443 }; 444 445 can5: can@e083c000 { 446 compatible = "bosch,m_can"; 447 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 448 reg-names = "m_can", "message_ram"; 449 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 451 interrupt-names = "int0", "int1"; 452 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 453 clock-names = "hclk", "cclk"; 454 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 455 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 456 assigned-clock-rates = <40000000>; 457 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 458 status = "disabled"; 459 }; 460 461 adc: adc@e1000000 { 462 compatible = "microchip,sama7g5-adc"; 463 reg = <0xe1000000 0x200>; 464 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&pmc PMC_TYPE_GCK 26>; 466 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 467 assigned-clock-rates = <100000000>; 468 clock-names = "adc_clk"; 469 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 470 dma-names = "rx"; 471 atmel,min-sample-rate-hz = <200000>; 472 atmel,max-sample-rate-hz = <20000000>; 473 atmel,startup-time-ms = <4>; 474 #io-channel-cells = <1>; 475 nvmem-cells = <&temperature_calib>; 476 nvmem-cell-names = "temperature_calib"; 477 status = "disabled"; 478 }; 479 480 sdmmc0: mmc@e1204000 { 481 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 482 reg = <0xe1204000 0x4000>; 483 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 485 clock-names = "hclock", "multclk"; 486 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 487 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 488 assigned-clock-rates = <200000000>; 489 microchip,sdcal-inverted; 490 status = "disabled"; 491 }; 492 493 sdmmc1: mmc@e1208000 { 494 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 495 reg = <0xe1208000 0x4000>; 496 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 498 clock-names = "hclock", "multclk"; 499 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 500 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 501 assigned-clock-rates = <200000000>; 502 microchip,sdcal-inverted; 503 status = "disabled"; 504 }; 505 506 sdmmc2: mmc@e120c000 { 507 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 508 reg = <0xe120c000 0x4000>; 509 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 511 clock-names = "hclock", "multclk"; 512 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 513 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 514 assigned-clock-rates = <200000000>; 515 microchip,sdcal-inverted; 516 status = "disabled"; 517 }; 518 519 csi2dc: csi2dc@e1404000 { 520 compatible = "microchip,sama7g5-csi2dc"; 521 reg = <0xe1404000 0x500>; 522 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; 523 clock-names = "pclk", "scck"; 524 assigned-clocks = <&xisc>; 525 assigned-clock-rates = <266000000>; 526 status = "disabled"; 527 528 ports { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 port@0 { 532 reg = <0>; 533 csi2dc_in: endpoint { 534 }; 535 }; 536 537 port@1 { 538 reg = <1>; 539 csi2dc_out: endpoint { 540 bus-width = <14>; 541 hsync-active = <1>; 542 vsync-active = <1>; 543 remote-endpoint = <&xisc_in>; 544 }; 545 }; 546 }; 547 }; 548 549 xisc: xisc@e1408000 { 550 compatible = "microchip,sama7g5-isc"; 551 reg = <0xe1408000 0x2000>; 552 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 554 clock-names = "hclock"; 555 #clock-cells = <0>; 556 clock-output-names = "isc-mck"; 557 status = "disabled"; 558 559 port { 560 xisc_in: endpoint { 561 bus-type = <5>; /* Parallel */ 562 bus-width = <14>; 563 hsync-active = <1>; 564 vsync-active = <1>; 565 remote-endpoint = <&csi2dc_out>; 566 }; 567 }; 568 }; 569 570 pwm: pwm@e1604000 { 571 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 572 reg = <0xe1604000 0x4000>; 573 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 574 #pwm-cells = <3>; 575 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 576 status = "disabled"; 577 }; 578 579 pdmc0: sound@e1608000 { 580 compatible = "microchip,sama7g5-pdmc"; 581 reg = <0xe1608000 0x1000>; 582 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 583 #sound-dai-cells = <0>; 584 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 585 dma-names = "rx"; 586 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 587 clock-names = "pclk", "gclk"; 588 status = "disabled"; 589 }; 590 591 pdmc1: sound@e160c000 { 592 compatible = "microchip,sama7g5-pdmc"; 593 reg = <0xe160c000 0x1000>; 594 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 595 #sound-dai-cells = <0>; 596 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 597 dma-names = "rx"; 598 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 599 clock-names = "pclk", "gclk"; 600 status = "disabled"; 601 }; 602 603 spdifrx: spdifrx@e1614000 { 604 #sound-dai-cells = <0>; 605 compatible = "microchip,sama7g5-spdifrx"; 606 reg = <0xe1614000 0x4000>; 607 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 608 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 609 dma-names = "rx"; 610 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 611 clock-names = "pclk", "gclk"; 612 status = "disabled"; 613 }; 614 615 spdiftx: spdiftx@e1618000 { 616 #sound-dai-cells = <0>; 617 compatible = "microchip,sama7g5-spdiftx"; 618 reg = <0xe1618000 0x4000>; 619 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 620 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 621 dma-names = "tx"; 622 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 623 clock-names = "pclk", "gclk"; 624 }; 625 626 i2s0: i2s@e161c000 { 627 compatible = "microchip,sama7g5-i2smcc"; 628 #sound-dai-cells = <0>; 629 reg = <0xe161c000 0x4000>; 630 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 631 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 632 dma-names = "tx", "rx"; 633 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 634 clock-names = "pclk", "gclk"; 635 status = "disabled"; 636 }; 637 638 i2s1: i2s@e1620000 { 639 compatible = "microchip,sama7g5-i2smcc"; 640 #sound-dai-cells = <0>; 641 reg = <0xe1620000 0x4000>; 642 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 643 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 644 dma-names = "tx", "rx"; 645 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 646 clock-names = "pclk", "gclk"; 647 status = "disabled"; 648 }; 649 650 eic: interrupt-controller@e1628000 { 651 compatible = "microchip,sama7g5-eic"; 652 reg = <0xe1628000 0xec>; 653 interrupt-parent = <&gic>; 654 interrupt-controller; 655 #interrupt-cells = <2>; 656 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 659 clock-names = "pclk"; 660 status = "disabled"; 661 }; 662 663 pit64b0: timer@e1800000 { 664 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 665 reg = <0xe1800000 0x4000>; 666 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 668 clock-names = "pclk", "gclk"; 669 }; 670 671 pit64b1: timer@e1804000 { 672 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 673 reg = <0xe1804000 0x4000>; 674 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 676 clock-names = "pclk", "gclk"; 677 }; 678 679 aes: crypto@e1810000 { 680 compatible = "atmel,at91sam9g46-aes"; 681 reg = <0xe1810000 0x100>; 682 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 684 clock-names = "aes_clk"; 685 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 686 <&dma0 AT91_XDMAC_DT_PERID(2)>; 687 dma-names = "tx", "rx"; 688 }; 689 690 sha: crypto@e1814000 { 691 compatible = "atmel,at91sam9g46-sha"; 692 reg = <0xe1814000 0x100>; 693 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 695 clock-names = "sha_clk"; 696 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 697 dma-names = "tx"; 698 }; 699 700 flx0: flexcom@e1818000 { 701 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 702 reg = <0xe1818000 0x200>; 703 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 704 #address-cells = <1>; 705 #size-cells = <1>; 706 ranges = <0x0 0xe1818000 0x800>; 707 status = "disabled"; 708 709 uart0: serial@200 { 710 compatible = "atmel,at91sam9260-usart"; 711 reg = <0x200 0x200>; 712 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 713 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 715 clock-names = "usart"; 716 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 717 <&dma1 AT91_XDMAC_DT_PERID(5)>; 718 dma-names = "tx", "rx"; 719 atmel,use-dma-rx; 720 atmel,use-dma-tx; 721 status = "disabled"; 722 }; 723 }; 724 725 flx1: flexcom@e181c000 { 726 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 727 reg = <0xe181c000 0x200>; 728 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 729 #address-cells = <1>; 730 #size-cells = <1>; 731 ranges = <0x0 0xe181c000 0x800>; 732 status = "disabled"; 733 734 i2c1: i2c@600 { 735 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 736 reg = <0x600 0x200>; 737 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 741 atmel,fifo-size = <32>; 742 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 743 <&dma0 AT91_XDMAC_DT_PERID(7)>; 744 dma-names = "tx", "rx"; 745 status = "disabled"; 746 }; 747 }; 748 749 flx3: flexcom@e1824000 { 750 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 751 reg = <0xe1824000 0x200>; 752 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 ranges = <0x0 0xe1824000 0x800>; 756 status = "disabled"; 757 758 uart3: serial@200 { 759 compatible = "atmel,at91sam9260-usart"; 760 reg = <0x200 0x200>; 761 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 762 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 764 clock-names = "usart"; 765 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 766 <&dma1 AT91_XDMAC_DT_PERID(11)>; 767 dma-names = "tx", "rx"; 768 atmel,use-dma-rx; 769 atmel,use-dma-tx; 770 status = "disabled"; 771 }; 772 }; 773 774 trng: rng@e2010000 { 775 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 776 reg = <0xe2010000 0x100>; 777 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 779 status = "disabled"; 780 }; 781 782 tdes: crypto@e2014000 { 783 compatible = "atmel,at91sam9g46-tdes"; 784 reg = <0xe2014000 0x100>; 785 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 787 clock-names = "tdes_clk"; 788 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 789 <&dma0 AT91_XDMAC_DT_PERID(53)>; 790 dma-names = "tx", "rx"; 791 }; 792 793 flx4: flexcom@e2018000 { 794 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 795 reg = <0xe2018000 0x200>; 796 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 797 #address-cells = <1>; 798 #size-cells = <1>; 799 ranges = <0x0 0xe2018000 0x800>; 800 status = "disabled"; 801 802 uart4: serial@200 { 803 compatible = "atmel,at91sam9260-usart"; 804 reg = <0x200 0x200>; 805 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 806 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 808 clock-names = "usart"; 809 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 810 <&dma1 AT91_XDMAC_DT_PERID(13)>; 811 dma-names = "tx", "rx"; 812 atmel,use-dma-rx; 813 atmel,use-dma-tx; 814 atmel,fifo-size = <16>; 815 status = "disabled"; 816 }; 817 }; 818 819 flx7: flexcom@e2024000 { 820 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 821 reg = <0xe2024000 0x200>; 822 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 823 #address-cells = <1>; 824 #size-cells = <1>; 825 ranges = <0x0 0xe2024000 0x800>; 826 status = "disabled"; 827 828 uart7: serial@200 { 829 compatible = "atmel,at91sam9260-usart"; 830 reg = <0x200 0x200>; 831 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 832 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 834 clock-names = "usart"; 835 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 836 <&dma1 AT91_XDMAC_DT_PERID(19)>; 837 dma-names = "tx", "rx"; 838 atmel,use-dma-rx; 839 atmel,use-dma-tx; 840 atmel,fifo-size = <16>; 841 status = "disabled"; 842 }; 843 }; 844 845 gmac0: ethernet@e2800000 { 846 compatible = "microchip,sama7g5-gem"; 847 reg = <0xe2800000 0x1000>; 848 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 855 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 856 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 857 assigned-clock-rates = <125000000>; 858 status = "disabled"; 859 }; 860 861 gmac1: ethernet@e2804000 { 862 compatible = "microchip,sama7g5-emac"; 863 reg = <0xe2804000 0x1000>; 864 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 867 clock-names = "pclk", "hclk"; 868 status = "disabled"; 869 }; 870 871 dma0: dma-controller@e2808000 { 872 compatible = "microchip,sama7g5-dma"; 873 reg = <0xe2808000 0x1000>; 874 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 875 #dma-cells = <1>; 876 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 877 clock-names = "dma_clk"; 878 status = "disabled"; 879 }; 880 881 dma1: dma-controller@e280c000 { 882 compatible = "microchip,sama7g5-dma"; 883 reg = <0xe280c000 0x1000>; 884 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 885 #dma-cells = <1>; 886 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 887 clock-names = "dma_clk"; 888 status = "disabled"; 889 }; 890 891 /* Place dma2 here despite it's address */ 892 dma2: dma-controller@e1200000 { 893 compatible = "microchip,sama7g5-dma"; 894 reg = <0xe1200000 0x1000>; 895 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 896 #dma-cells = <1>; 897 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 898 clock-names = "dma_clk"; 899 dma-requests = <0>; 900 status = "disabled"; 901 }; 902 903 tcb0: timer@e2814000 { 904 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 reg = <0xe2814000 0x100>; 908 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 910 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 911 }; 912 913 flx8: flexcom@e2818000 { 914 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 915 reg = <0xe2818000 0x200>; 916 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges = <0x0 0xe2818000 0x800>; 920 status = "disabled"; 921 922 i2c8: i2c@600 { 923 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 924 reg = <0x600 0x200>; 925 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 929 atmel,fifo-size = <32>; 930 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 931 <&dma0 AT91_XDMAC_DT_PERID(21)>; 932 dma-names = "tx", "rx"; 933 status = "disabled"; 934 }; 935 }; 936 937 flx9: flexcom@e281c000 { 938 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 939 reg = <0xe281c000 0x200>; 940 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 941 #address-cells = <1>; 942 #size-cells = <1>; 943 ranges = <0x0 0xe281c000 0x800>; 944 status = "disabled"; 945 946 i2c9: i2c@600 { 947 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 948 reg = <0x600 0x200>; 949 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 953 atmel,fifo-size = <32>; 954 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 955 <&dma0 AT91_XDMAC_DT_PERID(23)>; 956 dma-names = "tx", "rx"; 957 status = "disabled"; 958 }; 959 }; 960 961 flx10: flexcom@e2820000 { 962 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 963 reg = <0xe2820000 0x200>; 964 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 965 #address-cells = <1>; 966 #size-cells = <1>; 967 ranges = <0x0 0xe2820000 0x800>; 968 status = "disabled"; 969 970 i2c10: i2c@600 { 971 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 972 reg = <0x600 0x200>; 973 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 977 atmel,fifo-size = <32>; 978 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 979 <&dma0 AT91_XDMAC_DT_PERID(25)>; 980 dma-names = "tx", "rx"; 981 status = "disabled"; 982 }; 983 }; 984 985 flx11: flexcom@e2824000 { 986 compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; 987 reg = <0xe2824000 0x200>; 988 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 989 #address-cells = <1>; 990 #size-cells = <1>; 991 ranges = <0x0 0xe2824000 0x800>; 992 status = "disabled"; 993 994 spi11: spi@400 { 995 compatible = "atmel,at91rm9200-spi"; 996 reg = <0x400 0x200>; 997 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 999 clock-names = "spi_clk"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 atmel,fifo-size = <32>; 1003 dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, 1004 <&dma0 AT91_XDMAC_DT_PERID(27)>; 1005 dma-names = "tx", "rx"; 1006 status = "disabled"; 1007 }; 1008 }; 1009 1010 uddrc: uddrc@e3800000 { 1011 compatible = "microchip,sama7g5-uddrc"; 1012 reg = <0xe3800000 0x4000>; 1013 }; 1014 1015 ddr3phy: ddr3phy@e3804000 { 1016 compatible = "microchip,sama7g5-ddr3phy"; 1017 reg = <0xe3804000 0x1000>; 1018 }; 1019 1020 otpc: efuse@e8c00000 { 1021 compatible = "microchip,sama7g5-otpc", "syscon"; 1022 reg = <0xe8c00000 0x100>; 1023 #address-cells = <1>; 1024 #size-cells = <1>; 1025 1026 temperature_calib: calib@1 { 1027 reg = <OTP_PKT(1) 76>; 1028 }; 1029 }; 1030 1031 gic: interrupt-controller@e8c11000 { 1032 compatible = "arm,cortex-a7-gic"; 1033 #interrupt-cells = <3>; 1034 #address-cells = <0>; 1035 interrupt-controller; 1036 reg = <0xe8c11000 0x1000>, 1037 <0xe8c12000 0x2000>; 1038 }; 1039 }; 1040}; 1041