1359575Sdim// SPDX-License-Identifier: GPL-2.0-only 2359575Sdim/* 3359575Sdim * Copyright 2011-2012 Calxeda, Inc. 4359575Sdim */ 5359575Sdim 6359575Sdim/dts-v1/; 7359575Sdim 8359575Sdim/* First 4KB has pen for secondary cores. */ 9359575Sdim/memreserve/ 0x00000000 0x0001000; 10359575Sdim 11359575Sdim/ { 12359575Sdim model = "Calxeda Highbank"; 13359575Sdim compatible = "calxeda,highbank"; 14359575Sdim #address-cells = <1>; 15359575Sdim #size-cells = <1>; 16359575Sdim 17359575Sdim cpus { 18359575Sdim #address-cells = <1>; 19359575Sdim #size-cells = <0>; 20359575Sdim 21359575Sdim cpu@900 { 22359575Sdim compatible = "arm,cortex-a9"; 23359575Sdim device_type = "cpu"; 24359575Sdim reg = <0x900>; 25359575Sdim next-level-cache = <&L2>; 26359575Sdim clocks = <&a9pll>; 27359575Sdim clock-names = "cpu"; 28359575Sdim operating-points = < 29359575Sdim /* kHz ignored */ 30359575Sdim 1300000 1000000 31359575Sdim 1200000 1000000 32359575Sdim 1100000 1000000 33359575Sdim 800000 1000000 34359575Sdim 400000 1000000 35359575Sdim 200000 1000000 36359575Sdim >; 37359575Sdim clock-latency = <100000>; 38359575Sdim }; 39359575Sdim 40359575Sdim cpu@901 { 41359575Sdim compatible = "arm,cortex-a9"; 42359575Sdim device_type = "cpu"; 43359575Sdim reg = <0x901>; 44359575Sdim next-level-cache = <&L2>; 45359575Sdim clocks = <&a9pll>; 46359575Sdim clock-names = "cpu"; 47359575Sdim operating-points = < 48359575Sdim /* kHz ignored */ 49359575Sdim 1300000 1000000 50359575Sdim 1200000 1000000 51359575Sdim 1100000 1000000 52359575Sdim 800000 1000000 53359575Sdim 400000 1000000 54359575Sdim 200000 1000000 55359575Sdim >; 56359575Sdim clock-latency = <100000>; 57359575Sdim }; 58359575Sdim 59359575Sdim cpu@902 { 60359575Sdim compatible = "arm,cortex-a9"; 61359575Sdim device_type = "cpu"; 62359575Sdim reg = <0x902>; 63359575Sdim next-level-cache = <&L2>; 64359575Sdim clocks = <&a9pll>; 65359575Sdim clock-names = "cpu"; 66359575Sdim operating-points = < 67359575Sdim /* kHz ignored */ 68359575Sdim 1300000 1000000 69359575Sdim 1200000 1000000 70359575Sdim 1100000 1000000 71359575Sdim 800000 1000000 72359575Sdim 400000 1000000 73359575Sdim 200000 1000000 74359575Sdim >; 75359575Sdim clock-latency = <100000>; 76359575Sdim }; 77359575Sdim 78359575Sdim cpu@903 { 79359575Sdim compatible = "arm,cortex-a9"; 80359575Sdim device_type = "cpu"; 81359575Sdim reg = <0x903>; 82359575Sdim next-level-cache = <&L2>; 83359575Sdim clocks = <&a9pll>; 84359575Sdim clock-names = "cpu"; 85359575Sdim operating-points = < 86359575Sdim /* kHz ignored */ 87359575Sdim 1300000 1000000 88359575Sdim 1200000 1000000 89359575Sdim 1100000 1000000 90359575Sdim 800000 1000000 91359575Sdim 400000 1000000 92359575Sdim 200000 1000000 93359575Sdim >; 94359575Sdim clock-latency = <100000>; 95359575Sdim }; 96359575Sdim }; 97359575Sdim 98359575Sdim memory@0 { 99359575Sdim name = "memory"; 100359575Sdim device_type = "memory"; 101359575Sdim reg = <0x00000000 0xff900000>; 102359575Sdim }; 103359575Sdim 104359575Sdim soc { 105359575Sdim ranges = <0x00000000 0x00000000 0xffffffff>; 106359575Sdim 107359575Sdim memory-controller@fff00000 { 108359575Sdim compatible = "calxeda,hb-ddr-ctrl"; 109359575Sdim reg = <0xfff00000 0x1000>; 110359575Sdim interrupts = <0 91 4>; 111359575Sdim }; 112359575Sdim 113359575Sdim timer@fff10600 { 114359575Sdim compatible = "arm,cortex-a9-twd-timer"; 115359575Sdim reg = <0xfff10600 0x20>; 116359575Sdim interrupts = <1 13 0xf01>; 117359575Sdim clocks = <&a9periphclk>; 118359575Sdim }; 119359575Sdim 120359575Sdim watchdog@fff10620 { 121359575Sdim compatible = "arm,cortex-a9-twd-wdt"; 122359575Sdim reg = <0xfff10620 0x20>; 123359575Sdim interrupts = <1 14 0xf01>; 124359575Sdim clocks = <&a9periphclk>; 125359575Sdim }; 126359575Sdim 127359575Sdim intc: interrupt-controller@fff11000 { 128359575Sdim compatible = "arm,cortex-a9-gic"; 129359575Sdim #interrupt-cells = <3>; 130359575Sdim interrupt-controller; 131359575Sdim reg = <0xfff11000 0x1000>, 132359575Sdim <0xfff10100 0x100>; 133359575Sdim }; 134359575Sdim 135359575Sdim L2: cache-controller { 136359575Sdim compatible = "arm,pl310-cache"; 137359575Sdim reg = <0xfff12000 0x1000>; 138359575Sdim interrupts = <0 70 4>; 139359575Sdim cache-unified; 140359575Sdim cache-level = <2>; 141359575Sdim }; 142359575Sdim 143359575Sdim pmu { 144359575Sdim compatible = "arm,cortex-a9-pmu"; 145359575Sdim interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; 146359575Sdim }; 147359575Sdim 148359575Sdim 149359575Sdim sregs@fff3c200 { 150359575Sdim compatible = "calxeda,hb-sregs-l2-ecc"; 151359575Sdim reg = <0xfff3c200 0x100>; 152359575Sdim interrupts = <0 71 4>, <0 72 4>; 153359575Sdim }; 154359575Sdim 155359575Sdim }; 156359575Sdim}; 157359575Sdim 158359575Sdim/include/ "ecx-common.dtsi" 159359575Sdim