1178476Sjb/*
2178476Sjb * Copyright 2016 Linaro Ltd
3178476Sjb *
4178476Sjb * Permission is hereby granted, free of charge, to any person obtaining a copy
5178476Sjb * of this software and associated documentation files (the "Software"), to deal
6178476Sjb * in the Software without restriction, including without limitation the rights
7178476Sjb * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8178476Sjb * copies of the Software, and to permit persons to whom the Software is
9178476Sjb * furnished to do so, subject to the following conditions:
10178476Sjb *
11178476Sjb * The above copyright notice and this permission notice shall be included in
12178476Sjb * all copies or substantial portions of the Software.
13178476Sjb *
14178476Sjb * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15178476Sjb * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16178476Sjb * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17178476Sjb * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18178476Sjb * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19178476Sjb * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20178476Sjb * THE SOFTWARE.
21178476Sjb */
22178476Sjb
23178476Sjb#include <dt-bindings/interrupt-controller/irq.h>
24178476Sjb#include <dt-bindings/gpio/gpio.h>
25178476Sjb
26178476Sjb/ {
27178476Sjb	#address-cells = <1>;
28178476Sjb	#size-cells = <1>;
29178476Sjb	compatible = "arm,realview-eb";
30178476Sjb
31178476Sjb	chosen { };
32178476Sjb
33178476Sjb	aliases {
34178476Sjb		serial0 = &serial0;
35178476Sjb		serial1 = &serial1;
36178476Sjb		serial2 = &serial2;
37178476Sjb		serial3 = &serial3;
38178476Sjb		i2c0 = &i2c;
39178476Sjb	};
40178476Sjb
41178476Sjb	memory {
42178476Sjb		device_type = "memory";
43178476Sjb		/* 128 MiB memory @ 0x0 */
44178476Sjb		reg = <0x00000000 0x08000000>;
45178476Sjb	};
46178476Sjb
47178476Sjb	/* The voltage to the MMC card is hardwired at 3.3V */
48178476Sjb	vmmc: fixedregulator@0 {
49178476Sjb		compatible = "regulator-fixed";
50178476Sjb		regulator-name = "vmmc";
51178476Sjb		regulator-min-microvolt = <3300000>;
52178476Sjb		regulator-max-microvolt = <3300000>;
53178476Sjb		regulator-boot-on;
54178476Sjb        };
55178476Sjb
56178476Sjb	xtal24mhz: xtal24mhz@24M {
57178476Sjb		#clock-cells = <0>;
58178476Sjb		compatible = "fixed-clock";
59178476Sjb		clock-frequency = <24000000>;
60178476Sjb	};
61178476Sjb
62178476Sjb	timclk: timclk@1M {
63178476Sjb		#clock-cells = <0>;
64178476Sjb		compatible = "fixed-factor-clock";
65178476Sjb		clock-div = <24>;
66178476Sjb		clock-mult = <1>;
67178476Sjb		clocks = <&xtal24mhz>;
68178476Sjb	};
69178476Sjb
70178476Sjb	mclk: mclk@24M {
71178476Sjb		#clock-cells = <0>;
72178476Sjb		compatible = "fixed-factor-clock";
73178476Sjb		clock-div = <1>;
74178476Sjb		clock-mult = <1>;
75178476Sjb		clocks = <&xtal24mhz>;
76178476Sjb	};
77178476Sjb
78178476Sjb	kmiclk: kmiclk@24M {
79178476Sjb		#clock-cells = <0>;
80178476Sjb		compatible = "fixed-factor-clock";
81178476Sjb		clock-div = <1>;
82178476Sjb		clock-mult = <1>;
83178476Sjb		clocks = <&xtal24mhz>;
84178476Sjb	};
85178476Sjb
86178476Sjb	sspclk: sspclk@24M {
87178476Sjb		#clock-cells = <0>;
88178476Sjb		compatible = "fixed-factor-clock";
89178476Sjb		clock-div = <1>;
90178476Sjb		clock-mult = <1>;
91178476Sjb		clocks = <&xtal24mhz>;
92178476Sjb	};
93178476Sjb
94178476Sjb	uartclk: uartclk@24M {
95178476Sjb		#clock-cells = <0>;
96178476Sjb		compatible = "fixed-factor-clock";
97178476Sjb		clock-div = <1>;
98178476Sjb		clock-mult = <1>;
99178476Sjb		clocks = <&xtal24mhz>;
100	};
101
102	wdogclk: wdogclk@24M {
103		#clock-cells = <0>;
104		compatible = "fixed-factor-clock";
105		clock-div = <1>;
106		clock-mult = <1>;
107		clocks = <&xtal24mhz>;
108	};
109
110	/* FIXME: this actually hangs off the PLL clocks */
111	pclk: pclk@0 {
112		#clock-cells = <0>;
113		compatible = "fixed-clock";
114		clock-frequency = <0>;
115	};
116
117	flash0@40000000 {
118		/* 2 * 32MiB NOR Flash memory */
119		compatible = "arm,versatile-flash", "cfi-flash";
120		reg = <0x40000000 0x04000000>;
121		bank-width = <4>;
122		partitions {
123			compatible = "arm,arm-firmware-suite";
124		};
125	};
126
127	flash1@44000000 {
128		/* 2 * 32MiB NOR Flash memory */
129		compatible = "arm,versatile-flash", "cfi-flash";
130		reg = <0x44000000 0x04000000>;
131		bank-width = <4>;
132		partitions {
133			compatible = "arm,arm-firmware-suite";
134		};
135	};
136
137	/* SMSC LAN91C111 ethernet with PHY and EEPROM */
138	ethernet: ethernet@4e000000 {
139		compatible = "smsc,lan91c111";
140		reg = <0x4e000000 0x10000>;
141		/*
142		 * This means the adapter can be accessed with 8, 16 or
143		 * 32 bit reads/writes.
144		 */
145		reg-io-width = <7>;
146	};
147
148	usb: usb@4f000000 {
149		compatible = "nxp,usb-isp1761";
150		reg = <0x4f000000 0x20000>;
151		dr_mode = "peripheral";
152	};
153
154	bridge {
155		compatible = "ti,ths8134a", "ti,ths8134";
156		#address-cells = <1>;
157		#size-cells = <0>;
158
159		ports {
160			#address-cells = <1>;
161			#size-cells = <0>;
162
163			port@0 {
164				reg = <0>;
165
166				vga_bridge_in: endpoint {
167					remote-endpoint = <&clcd_pads>;
168				};
169			};
170
171			port@1 {
172				reg = <1>;
173
174				vga_bridge_out: endpoint {
175					remote-endpoint = <&vga_con_in>;
176				};
177			};
178		};
179	};
180
181	vga {
182		compatible = "vga-connector";
183
184		port {
185			vga_con_in: endpoint {
186				remote-endpoint = <&vga_bridge_out>;
187			};
188		};
189	};
190
191	/* These peripherals are inside the FPGA */
192	fpga {
193		#address-cells = <1>;
194		#size-cells = <1>;
195		compatible = "simple-bus";
196		ranges;
197
198		syscon: syscon@10000000 {
199			compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
200			reg = <0x10000000 0x1000>;
201			ranges = <0x0 0x10000000 0x1000>;
202			#address-cells = <1>;
203			#size-cells = <1>;
204
205			led@8,0 {
206				compatible = "register-bit-led";
207				reg = <0x08 0x04>;
208				offset = <0x08>;
209				mask = <0x01>;
210				label = "versatile:0";
211				linux,default-trigger = "heartbeat";
212				default-state = "on";
213			};
214			led@8,1 {
215				compatible = "register-bit-led";
216				reg = <0x08 0x04>;
217				offset = <0x08>;
218				mask = <0x02>;
219				label = "versatile:1";
220				linux,default-trigger = "mmc0";
221				default-state = "off";
222			};
223			led@8,2 {
224				compatible = "register-bit-led";
225				reg = <0x08 0x04>;
226				offset = <0x08>;
227				mask = <0x04>;
228				label = "versatile:2";
229				linux,default-trigger = "cpu0";
230				default-state = "off";
231			};
232			led@8,3 {
233				compatible = "register-bit-led";
234				reg = <0x08 0x04>;
235				offset = <0x08>;
236				mask = <0x08>;
237				label = "versatile:3";
238				default-state = "off";
239			};
240			led@8,4 {
241				compatible = "register-bit-led";
242				reg = <0x08 0x04>;
243				offset = <0x08>;
244				mask = <0x10>;
245				label = "versatile:4";
246				default-state = "off";
247			};
248			led@8,5 {
249				compatible = "register-bit-led";
250				reg = <0x08 0x04>;
251				offset = <0x08>;
252				mask = <0x20>;
253				label = "versatile:5";
254				default-state = "off";
255			};
256			led@8,6 {
257				compatible = "register-bit-led";
258				reg = <0x08 0x04>;
259				offset = <0x08>;
260				mask = <0x40>;
261				label = "versatile:6";
262				default-state = "off";
263			};
264			led@8,7 {
265				compatible = "register-bit-led";
266				reg = <0x08 0x04>;
267				offset = <0x08>;
268				mask = <0x80>;
269				label = "versatile:7";
270				default-state = "off";
271			};
272			oscclk0: clock-controller@c {
273				compatible = "arm,syscon-icst307";
274				reg = <0x0c 0x04>;
275				#clock-cells = <0>;
276				lock-offset = <0x20>;
277				vco-offset = <0x0C>;
278				clocks = <&xtal24mhz>;
279			};
280			oscclk1: clock-controller@10 {
281				compatible = "arm,syscon-icst307";
282				reg = <0x10 0x04>;
283				#clock-cells = <0>;
284				lock-offset = <0x20>;
285				vco-offset = <0x10>;
286				clocks = <&xtal24mhz>;
287			};
288			oscclk2: clock-controller@14 {
289				compatible = "arm,syscon-icst307";
290				reg = <0x14 0x04>;
291				#clock-cells = <0>;
292				lock-offset = <0x20>;
293				vco-offset = <0x14>;
294				clocks = <&xtal24mhz>;
295			};
296			oscclk3: clock-controller@18 {
297				compatible = "arm,syscon-icst307";
298				reg = <0x18 0x04>;
299				#clock-cells = <0>;
300				lock-offset = <0x20>;
301				vco-offset = <0x18>;
302				clocks = <&xtal24mhz>;
303			};
304			oscclk4: clock-controller@1c {
305				compatible = "arm,syscon-icst307";
306				reg = <0x1c 0x04>;
307				#clock-cells = <0>;
308				lock-offset = <0x20>;
309				vco-offset = <0x1c>;
310				clocks = <&xtal24mhz>;
311			};
312		};
313
314		i2c: i2c@10002000 {
315			#address-cells = <1>;
316			#size-cells = <0>;
317			compatible = "arm,versatile-i2c";
318			reg = <0x10002000 0x1000>;
319
320			rtc@68 {
321				compatible = "dallas,ds1338";
322				reg = <0x68>;
323			};
324		};
325
326		aaci: aaci@10004000 {
327			compatible = "arm,pl041", "arm,primecell";
328			reg = <0x10004000 0x1000>;
329			clocks = <&pclk>;
330			clock-names = "apb_pclk";
331		};
332
333		mmc: mmcsd@10005000 {
334			compatible = "arm,pl18x", "arm,primecell";
335			reg = <0x10005000 0x1000>;
336
337			/* Due to frequent FIFO overruns, use just 500 kHz */
338			max-frequency = <500000>;
339			bus-width = <4>;
340			cap-sd-highspeed;
341			cap-mmc-highspeed;
342			clocks = <&mclk>, <&pclk>;
343			clock-names = "mclk", "apb_pclk";
344			vmmc-supply = <&vmmc>;
345			cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
346			wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
347		};
348
349		kmi0: kmi@10006000 {
350			compatible = "arm,pl050", "arm,primecell";
351			reg = <0x10006000 0x1000>;
352			clocks = <&kmiclk>, <&pclk>;
353			clock-names = "KMIREFCLK", "apb_pclk";
354		};
355
356		kmi1: kmi@10007000 {
357			compatible = "arm,pl050", "arm,primecell";
358			reg = <0x10007000 0x1000>;
359			clocks = <&kmiclk>, <&pclk>;
360			clock-names = "KMIREFCLK", "apb_pclk";
361		};
362
363		charlcd: fpga_charlcd: charlcd@10008000 {
364			compatible = "arm,versatile-lcd";
365			reg = <0x10008000 0x1000>;
366			clocks = <&pclk>;
367			clock-names = "apb_pclk";
368		};
369
370		serial0: serial@10009000 {
371			compatible = "arm,pl011", "arm,primecell";
372			reg = <0x10009000 0x1000>;
373			clocks = <&uartclk>, <&pclk>;
374			clock-names = "uartclk", "apb_pclk";
375		};
376
377		serial1: serial@1000a000 {
378			compatible = "arm,pl011", "arm,primecell";
379			reg = <0x1000a000 0x1000>;
380			clocks = <&uartclk>, <&pclk>;
381			clock-names = "uartclk", "apb_pclk";
382		};
383
384		serial2: serial@1000b000 {
385			compatible = "arm,pl011", "arm,primecell";
386			reg = <0x1000b000 0x1000>;
387			clocks = <&uartclk>, <&pclk>;
388			clock-names = "uartclk", "apb_pclk";
389		};
390
391		serial3: serial@1000c000 {
392			compatible = "arm,pl011", "arm,primecell";
393			reg = <0x1000c000 0x1000>;
394			clocks = <&uartclk>, <&pclk>;
395			clock-names = "uartclk", "apb_pclk";
396		};
397
398		ssp: spi@1000d000 {
399			compatible = "arm,pl022", "arm,primecell";
400			reg = <0x1000d000 0x1000>;
401			clocks = <&sspclk>, <&pclk>;
402			clock-names = "sspclk", "apb_pclk";
403		};
404
405		wdog: watchdog@10010000 {
406			compatible = "arm,sp805", "arm,primecell";
407			reg = <0x10010000 0x1000>;
408			clocks = <&wdogclk>, <&pclk>;
409			clock-names = "wdog_clk", "apb_pclk";
410			status = "disabled";
411		};
412
413		timer01: timer@10011000 {
414			compatible = "arm,sp804", "arm,primecell";
415			reg = <0x10011000 0x1000>;
416			clocks = <&timclk>, <&timclk>, <&pclk>;
417			clock-names = "timer1", "timer2", "apb_pclk";
418		};
419
420		timer23: timer@10012000 {
421			compatible = "arm,sp804", "arm,primecell";
422			reg = <0x10012000 0x1000>;
423			clocks = <&timclk>, <&timclk>, <&pclk>;
424			clock-names = "timer1", "timer2", "apb_pclk";
425		};
426
427		gpio0: gpio@10013000 {
428			compatible = "arm,pl061", "arm,primecell";
429			reg = <0x10013000 0x1000>;
430			gpio-controller;
431			#gpio-cells = <2>;
432			interrupt-controller;
433			#interrupt-cells = <2>;
434			clocks = <&pclk>;
435			clock-names = "apb_pclk";
436		};
437
438		gpio1: gpio@10014000 {
439			compatible = "arm,pl061", "arm,primecell";
440			reg = <0x10014000 0x1000>;
441			gpio-controller;
442			#gpio-cells = <2>;
443			interrupt-controller;
444			#interrupt-cells = <2>;
445			clocks = <&pclk>;
446			clock-names = "apb_pclk";
447		};
448
449		gpio2: gpio@10015000 {
450			compatible = "arm,pl061", "arm,primecell";
451			reg = <0x10015000 0x1000>;
452			gpio-controller;
453			#gpio-cells = <2>;
454			interrupt-controller;
455			#interrupt-cells = <2>;
456			clocks = <&pclk>;
457			clock-names = "apb_pclk";
458		};
459
460		rtc: rtc@10017000 {
461			compatible = "arm,pl031", "arm,primecell";
462			reg = <0x10017000 0x1000>;
463			clocks = <&pclk>;
464			clock-names = "apb_pclk";
465		};
466
467		clcd: clcd@10020000 {
468			compatible = "arm,pl111", "arm,primecell";
469			reg = <0x10020000 0x1000>;
470			interrupt-names = "combined";
471			clocks = <&oscclk0>, <&pclk>;
472			clock-names = "clcdclk", "apb_pclk";
473			/* 1024x768 16bpp @65MHz works fine */
474			max-memory-bandwidth = <95000000>;
475
476			port {
477				clcd_pads: endpoint {
478					remote-endpoint = <&vga_bridge_in>;
479					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
480				};
481			};
482		};
483	};
484};
485