1// SPDX-License-Identifier: GPL-2.0
2/*
3 *  linux/arch/alpha/kernel/sys_wildfire.c
4 *
5 *  Wildfire support.
6 *
7 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
8 */
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/mm.h>
13#include <linux/sched.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/bitops.h>
17
18#include <asm/ptrace.h>
19#include <asm/dma.h>
20#include <asm/irq.h>
21#include <asm/mmu_context.h>
22#include <asm/io.h>
23#include <asm/core_wildfire.h>
24#include <asm/hwrpb.h>
25#include <asm/tlbflush.h>
26
27#include "proto.h"
28#include "irq_impl.h"
29#include "pci_impl.h"
30#include "machvec_impl.h"
31
32static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)];
33
34DEFINE_SPINLOCK(wildfire_irq_lock);
35
36static int doing_init_irq_hw = 0;
37
38static void
39wildfire_update_irq_hw(unsigned int irq)
40{
41	int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1);
42	int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1);
43	wildfire_pca *pca;
44	volatile unsigned long * enable0;
45
46	if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
47		if (!doing_init_irq_hw) {
48			printk(KERN_ERR "wildfire_update_irq_hw:"
49			       " got irq %d for non-existent PCA %d"
50			       " on QBB %d.\n",
51			       irq, pcano, qbbno);
52		}
53		return;
54	}
55
56	pca = WILDFIRE_pca(qbbno, pcano);
57	enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */
58
59	*enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano];
60	mb();
61	*enable0;
62}
63
64static void __init
65wildfire_init_irq_hw(void)
66{
67#if 0
68	register wildfire_pca * pca = WILDFIRE_pca(0, 0);
69	volatile unsigned long * enable0, * enable1, * enable2, *enable3;
70	volatile unsigned long * target0, * target1, * target2, *target3;
71
72	enable0 = (unsigned long *) &pca->pca_int[0].enable;
73	enable1 = (unsigned long *) &pca->pca_int[1].enable;
74	enable2 = (unsigned long *) &pca->pca_int[2].enable;
75	enable3 = (unsigned long *) &pca->pca_int[3].enable;
76
77	target0 = (unsigned long *) &pca->pca_int[0].target;
78	target1 = (unsigned long *) &pca->pca_int[1].target;
79	target2 = (unsigned long *) &pca->pca_int[2].target;
80	target3 = (unsigned long *) &pca->pca_int[3].target;
81
82	*enable0 = *enable1 = *enable2 = *enable3 = 0;
83
84	*target0 = (1UL<<8) | WILDFIRE_QBB(0);
85	*target1 = *target2 = *target3 = 0;
86
87	mb();
88
89	*enable0; *enable1; *enable2; *enable3;
90	*target0; *target1; *target2; *target3;
91
92#else
93	int i;
94
95	doing_init_irq_hw = 1;
96
97	/* Need to update only once for every possible PCA. */
98	for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA)
99		wildfire_update_irq_hw(i);
100
101	doing_init_irq_hw = 0;
102#endif
103}
104
105static void
106wildfire_enable_irq(struct irq_data *d)
107{
108	unsigned int irq = d->irq;
109
110	if (irq < 16)
111		i8259a_enable_irq(d);
112
113	spin_lock(&wildfire_irq_lock);
114	set_bit(irq, &cached_irq_mask);
115	wildfire_update_irq_hw(irq);
116	spin_unlock(&wildfire_irq_lock);
117}
118
119static void
120wildfire_disable_irq(struct irq_data *d)
121{
122	unsigned int irq = d->irq;
123
124	if (irq < 16)
125		i8259a_disable_irq(d);
126
127	spin_lock(&wildfire_irq_lock);
128	clear_bit(irq, &cached_irq_mask);
129	wildfire_update_irq_hw(irq);
130	spin_unlock(&wildfire_irq_lock);
131}
132
133static void
134wildfire_mask_and_ack_irq(struct irq_data *d)
135{
136	unsigned int irq = d->irq;
137
138	if (irq < 16)
139		i8259a_mask_and_ack_irq(d);
140
141	spin_lock(&wildfire_irq_lock);
142	clear_bit(irq, &cached_irq_mask);
143	wildfire_update_irq_hw(irq);
144	spin_unlock(&wildfire_irq_lock);
145}
146
147static struct irq_chip wildfire_irq_type = {
148	.name		= "WILDFIRE",
149	.irq_unmask	= wildfire_enable_irq,
150	.irq_mask	= wildfire_disable_irq,
151	.irq_mask_ack	= wildfire_mask_and_ack_irq,
152};
153
154static void __init
155wildfire_init_irq_per_pca(int qbbno, int pcano)
156{
157	int i, irq_bias;
158
159	irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
160		 + pcano * WILDFIRE_IRQ_PER_PCA;
161
162#if 0
163	unsigned long io_bias;
164
165	/* Only need the following for first PCI bus per PCA. */
166	io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
167
168	outb(0, DMA1_RESET_REG + io_bias);
169	outb(0, DMA2_RESET_REG + io_bias);
170	outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);
171	outb(0, DMA2_MASK_REG + io_bias);
172#endif
173
174#if 0
175	/* ??? Not sure how to do this, yet... */
176	init_i8259a_irqs(); /* ??? */
177#endif
178
179	for (i = 0; i < 16; ++i) {
180		if (i == 2)
181			continue;
182		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
183					 handle_level_irq);
184		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
185	}
186
187	irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
188				 handle_level_irq);
189	irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
190	for (i = 40; i < 64; ++i) {
191		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
192					 handle_level_irq);
193		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
194	}
195
196	if (request_irq(32 + irq_bias, no_action, 0, "isa_enable", NULL))
197		pr_err("Failed to register isa_enable interrupt\n");
198}
199
200static void __init
201wildfire_init_irq(void)
202{
203	int qbbno, pcano;
204
205#if 1
206	wildfire_init_irq_hw();
207	init_i8259a_irqs();
208#endif
209
210	for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
211	  if (WILDFIRE_QBB_EXISTS(qbbno)) {
212	    for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
213	      if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
214		wildfire_init_irq_per_pca(qbbno, pcano);
215	      }
216	    }
217	  }
218	}
219}
220
221static void
222wildfire_device_interrupt(unsigned long vector)
223{
224	int irq;
225
226	irq = (vector - 0x800) >> 4;
227
228	/*
229	 * bits 10-8:	source QBB ID
230	 * bits 7-6:	PCA
231	 * bits 5-0:	irq in PCA
232	 */
233
234	handle_irq(irq);
235	return;
236}
237
238/*
239 * PCI Fixup configuration.
240 *
241 * Summary per PCA (2 PCI or HIPPI buses):
242 *
243 * Bit      Meaning
244 * 0-15     ISA
245 *
246 *32        ISA summary
247 *33        SMI
248 *34        NMI
249 *36        builtin QLogic SCSI (or slot 0 if no IO module)
250 *40        Interrupt Line A from slot 2 PCI0
251 *41        Interrupt Line B from slot 2 PCI0
252 *42        Interrupt Line C from slot 2 PCI0
253 *43        Interrupt Line D from slot 2 PCI0
254 *44        Interrupt Line A from slot 3 PCI0
255 *45        Interrupt Line B from slot 3 PCI0
256 *46        Interrupt Line C from slot 3 PCI0
257 *47        Interrupt Line D from slot 3 PCI0
258 *
259 *48        Interrupt Line A from slot 4 PCI1
260 *49        Interrupt Line B from slot 4 PCI1
261 *50        Interrupt Line C from slot 4 PCI1
262 *51        Interrupt Line D from slot 4 PCI1
263 *52        Interrupt Line A from slot 5 PCI1
264 *53        Interrupt Line B from slot 5 PCI1
265 *54        Interrupt Line C from slot 5 PCI1
266 *55        Interrupt Line D from slot 5 PCI1
267 *56        Interrupt Line A from slot 6 PCI1
268 *57        Interrupt Line B from slot 6 PCI1
269 *58        Interrupt Line C from slot 6 PCI1
270 *50        Interrupt Line D from slot 6 PCI1
271 *60        Interrupt Line A from slot 7 PCI1
272 *61        Interrupt Line B from slot 7 PCI1
273 *62        Interrupt Line C from slot 7 PCI1
274 *63        Interrupt Line D from slot 7 PCI1
275 *
276 *
277 * IdSel
278 *   0	 Cypress Bridge I/O (ISA summary interrupt)
279 *   1	 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
280 *   2	 64 bit PCI 0 option slot 2
281 *   3	 64 bit PCI 0 option slot 3
282 *   4	 64 bit PCI 1 option slot 4
283 *   5	 64 bit PCI 1 option slot 5
284 *   6	 64 bit PCI 1 option slot 6
285 *   7	 64 bit PCI 1 option slot 7
286 */
287
288static int
289wildfire_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
290{
291	static char irq_tab[8][5] = {
292		/*INT    INTA   INTB   INTC   INTD */
293		{ -1,    -1,    -1,    -1,    -1}, /* IdSel 0 ISA Bridge */
294		{ 36,    36,    36+1, 36+2, 36+3}, /* IdSel 1 SCSI builtin */
295		{ 40,    40,    40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */
296		{ 44,    44,    44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */
297		{ 48,    48,    48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */
298		{ 52,    52,    52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */
299		{ 56,    56,    56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */
300		{ 60,    60,    60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */
301	};
302	long min_idsel = 0, max_idsel = 7, irqs_per_slot = 5;
303
304	struct pci_controller *hose = dev->sysdata;
305	int irq = COMMON_TABLE_LOOKUP;
306
307	if (irq > 0) {
308		int qbbno = hose->index >> 3;
309		int pcano = (hose->index >> 1) & 3;
310		irq += (qbbno << 8) + (pcano << 6);
311	}
312	return irq;
313}
314
315
316/*
317 * The System Vectors
318 */
319
320struct alpha_machine_vector wildfire_mv __initmv = {
321	.vector_name		= "WILDFIRE",
322	DO_EV6_MMU,
323	DO_DEFAULT_RTC,
324	DO_WILDFIRE_IO,
325	.machine_check		= wildfire_machine_check,
326	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
327	.min_io_address		= DEFAULT_IO_BASE,
328	.min_mem_address	= DEFAULT_MEM_BASE,
329
330	.nr_irqs		= WILDFIRE_NR_IRQS,
331	.device_interrupt	= wildfire_device_interrupt,
332
333	.init_arch		= wildfire_init_arch,
334	.init_irq		= wildfire_init_irq,
335	.init_rtc		= common_init_rtc,
336	.init_pci		= common_init_pci,
337	.kill_arch		= wildfire_kill_arch,
338	.pci_map_irq		= wildfire_map_irq,
339	.pci_swizzle		= common_swizzle,
340};
341ALIAS_MV(wildfire)
342