1==============================================
2spi_lm70llp :  LM70-LLP parport-to-SPI adapter
3==============================================
4
5Supported board/chip:
6
7  * National Semiconductor LM70 LLP evaluation board
8
9    Datasheet: https://www.ti.com/lit/gpn/lm70
10
11Author:
12        Kaiwan N Billimoria <kaiwan@designergraphix.com>
13
14Description
15-----------
16This driver provides glue code connecting a National Semiconductor LM70 LLP
17temperature sensor evaluation board to the kernel's SPI core subsystem.
18
19This is a SPI master controller driver. It can be used in conjunction with
20(layered under) the LM70 logical driver (a "SPI protocol driver").
21In effect, this driver turns the parallel port interface on the eval board
22into a SPI bus with a single device, which will be driven by the generic
23LM70 driver (drivers/hwmon/lm70.c).
24
25
26Hardware Interfacing
27--------------------
28The schematic for this particular board (the LM70EVAL-LLP) is
29available (on page 4) here:
30
31  https://download.datasheets.com/pdfs/documentation/nat/kit&board/lm70llpevalmanual.pdf
32
33The hardware interfacing on the LM70 LLP eval board is as follows:
34
35   ======== == =========   ==========
36   Parallel                 LM70 LLP
37     Port   .  Direction   JP2 Header
38   ======== == =========   ==========
39      D0     2      -         -
40      D1     3     -->      V+   5
41      D2     4     -->      V+   5
42      D3     5     -->      V+   5
43      D4     6     -->      V+   5
44      D5     7     -->      nCS  8
45      D6     8     -->      SCLK 3
46      D7     9     -->      SI/O 5
47     GND    25      -       GND  7
48    Select  13     <--      SI/O 1
49   ======== == =========   ==========
50
51Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
52is connected to both pin D7 (as Master Out) and Select (as Master In)
53using an arrangement that lets either the parport or the LM70 pull the
54pin low.  This can't be shared with true SPI devices, but other 3-wire
55devices might share the same SI/SO pin.
56
57The bitbanger routine in this driver (lm70_txrx) is called back from
58the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
59spi_write_then_read() call.  It performs Mode 0 (SPI/Microwire) bitbanging.
60The lm70 driver then interprets the resulting digital temperature value
61and exports it through sysfs.
62
63A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
64shows that the SI/O line from the LM70 chip is connected to the base of a
65transistor Q1 (and also a pullup, and a zener diode to D7); while the
66collector is tied to VCC.
67
68Interpreting this circuit, when the LM70 SI/O line is High (or tristate
69and not grounded by the host via D7), the transistor conducts and switches
70the collector to zero, which is reflected on pin 13 of the DB25 parport
71connector.  When SI/O is Low (driven by the LM70 or the host) on the other
72hand, the transistor is cut off and the voltage tied to its collector is
73reflected on pin 13 as a High level.
74
75So: the getmiso inline routine in this driver takes this fact into account,
76inverting the value read at pin 13.
77
78
79Thanks to
80---------
81
82- David Brownell for mentoring the SPI-side driver development.
83- Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
84- Nadir Billimoria for help interpreting the circuit schematic.
85