1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2020-21 Cadence
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Cadence XSPI Controller
9
10maintainers:
11  - Parshuram Thombare <pthombar@cadence.com>
12
13description: |
14  The XSPI controller allows SPI protocol communication in
15  single, dual, quad or octal wire transmission modes for
16  read/write access to slaves such as SPI-NOR flash.
17
18allOf:
19  - $ref: spi-controller.yaml#
20
21properties:
22  compatible:
23    const: cdns,xspi-nor
24
25  reg:
26    items:
27      - description: address and length of the controller register set
28      - description: address and length of the Slave DMA data port
29      - description: address and length of the auxiliary registers
30
31  reg-names:
32    items:
33      - const: io
34      - const: sdma
35      - const: aux
36
37  interrupts:
38    maxItems: 1
39
40required:
41  - compatible
42  - reg
43  - interrupts
44
45unevaluatedProperties: false
46
47examples:
48  - |
49    #include <dt-bindings/interrupt-controller/irq.h>
50    bus {
51        #address-cells = <2>;
52        #size-cells = <2>;
53
54        xspi: spi@a0010000 {
55            #address-cells = <1>;
56            #size-cells = <0>;
57            compatible = "cdns,xspi-nor";
58            reg = <0x0 0xa0010000 0x0 0x1040>,
59                  <0x0 0xb0000000 0x0 0x1000>,
60                  <0x0 0xa0020000 0x0 0x100>;
61            reg-names = "io", "sdma", "aux";
62            interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
63            interrupt-parent = <&gic>;
64
65            flash@0 {
66                compatible = "jedec,spi-nor";
67                spi-max-frequency = <75000000>;
68                reg = <0>;
69            };
70
71            flash@1 {
72                compatible = "jedec,spi-nor";
73                spi-max-frequency = <75000000>;
74                reg = <1>;
75            };
76        };
77    };
78