1210284Sjmallett# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 2232812Sjmallett# Copyright (C) 2019 Texas Instruments Incorporated 3215990Sjmallett%YAML 1.2 4210284Sjmallett--- 5210284Sjmallett$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml# 6215990Sjmallett$schema: http://devicetree.org/meta-schemas/core.yaml# 7215990Sjmallett 8215990Sjmalletttitle: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter 9210284Sjmallett 10215990Sjmallettmaintainers: 11215990Sjmallett - Andrew Davis <afd@ti.com> 12210284Sjmallett 13215990Sjmallettdescription: | 14215990Sjmallett The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital 15215990Sjmallett PDM microphones recording), high-performance audio, analog-to-digital 16215990Sjmallett converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140 17215990Sjmallett family supports line and microphone Inputs, and offers a programmable 18232812Sjmallett microphone bias or supply voltage generation. 19215990Sjmallett 20215990Sjmallett Specifications can be found at: 21215990Sjmallett https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf 22215990Sjmallett https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf 23215990Sjmallett https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf 24215990Sjmallett 25215990Sjmallettproperties: 26215990Sjmallett compatible: 27215990Sjmallett enum: 28215990Sjmallett - ti,tlv320adc3140 29232812Sjmallett - ti,tlv320adc5140 30215990Sjmallett - ti,tlv320adc6140 31215990Sjmallett 32215990Sjmallett reg: 33215990Sjmallett maxItems: 1 34215990Sjmallett description: | 35215990Sjmallett I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f 36215990Sjmallett 37215990Sjmallett reset-gpios: 38210284Sjmallett maxItems: 1 39210284Sjmallett description: | 40210284Sjmallett GPIO used for hardware reset. 41210284Sjmallett 42210284Sjmallett areg-supply: 43210284Sjmallett description: | 44210284Sjmallett Regulator with AVDD at 3.3V. If not defined then the internal regulator 45215990Sjmallett is enabled. 46210284Sjmallett 47210284Sjmallett ti,mic-bias-source: 48210284Sjmallett description: | 49210284Sjmallett Indicates the source for MIC Bias. 50210284Sjmallett 0 - Mic bias is set to VREF 51232812Sjmallett 1 - Mic bias is set to VREF �� 1.096 52210284Sjmallett 6 - Mic bias is set to AVDD 53210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32 54210284Sjmallett enum: [0, 1, 6] 55210284Sjmallett 56210284Sjmallett ti,vref-source: 57210284Sjmallett description: | 58210284Sjmallett Indicates the source for MIC Bias. 59210284Sjmallett 0 - Set VREF to 2.75V 60210284Sjmallett 1 - Set VREF to 2.5V 61210284Sjmallett 2 - Set VREF to 1.375V 62210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32 63210284Sjmallett enum: [0, 1, 2] 64210284Sjmallett 65210284Sjmallett ti,pdm-edge-select: 66210284Sjmallett description: | 67210284Sjmallett Defines the PDMCLK sampling edge configuration for the PDM inputs. This 68210284Sjmallett array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>. 69210284Sjmallett 70210284Sjmallett 0 - (default) Odd channel is latched on the negative edge and even 71210284Sjmallett channel is latched on the positive edge. 72210284Sjmallett 1 - Odd channel is latched on the positive edge and even channel is 73210284Sjmallett latched on the negative edge. 74210284Sjmallett 75210284Sjmallett PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data 76210284Sjmallett PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data 77210284Sjmallett PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data 78210284Sjmallett PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data 79210284Sjmallett 80210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32-array 81210284Sjmallett minItems: 1 82210284Sjmallett maxItems: 4 83210284Sjmallett items: 84210284Sjmallett maximum: 1 85210284Sjmallett default: [0, 0, 0, 0] 86210284Sjmallett 87210284Sjmallett ti,gpi-config: 88210284Sjmallett description: | 89210284Sjmallett Defines the configuration for the general purpose input pins (GPI). 90210284Sjmallett The array is defined as <GPI1 GPI2 GPI3 GPI4>. 91210284Sjmallett 92210284Sjmallett 0 - (default) disabled 93210284Sjmallett 1 - GPIX is configured as a general-purpose input (GPI) 94210284Sjmallett 2 - GPIX is configured as a master clock input (MCLK) 95210284Sjmallett 3 - GPIX is configured as an ASI input for daisy-chain (SDIN) 96210284Sjmallett 4 - GPIX is configured as a PDM data input for channel 1 and channel 97210284Sjmallett (PDMDIN1) 98210284Sjmallett 5 - GPIX is configured as a PDM data input for channel 3 and channel 99210284Sjmallett (PDMDIN2) 100210284Sjmallett 6 - GPIX is configured as a PDM data input for channel 5 and channel 101210284Sjmallett (PDMDIN3) 102210284Sjmallett 7 - GPIX is configured as a PDM data input for channel 7 and channel 103210284Sjmallett (PDMDIN4) 104210284Sjmallett 105210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32-array 106210284Sjmallett minItems: 1 107210284Sjmallett maxItems: 4 108210284Sjmallett items: 109210284Sjmallett maximum: 7 110210284Sjmallett default: [0, 0, 0, 0] 111210284Sjmallett 112210284Sjmallett ti,gpio-config: 113210284Sjmallett description: | 114210284Sjmallett Defines the configuration and output drive for the General Purpose 115210284Sjmallett Input and Output pin (GPIO1). Its value is a pair, the first value is for 116210284Sjmallett the configuration type and the second value is for the output drive 117210284Sjmallett type. The array is defined as <GPIO1_CFG GPIO1_DRV> 118210284Sjmallett 119210284Sjmallett configuration for the GPIO pin can be one of the following: 120210284Sjmallett 0 - disabled 121210284Sjmallett 1 - GPIO1 is configured as a general-purpose output (GPO) 122210284Sjmallett 2 - (default) GPIO1 is configured as a device interrupt output (IRQ) 123210284Sjmallett 3 - GPIO1 is configured as a secondary ASI output (SDOUT2) 124210284Sjmallett 4 - GPIO1 is configured as a PDM clock output (PDMCLK) 125210284Sjmallett 8 - GPIO1 is configured as an input to control when MICBIAS turns on or 126210284Sjmallett off (MICBIAS_EN) 127210284Sjmallett 9 - GPIO1 is configured as a general-purpose input (GPI) 128210284Sjmallett 10 - GPIO1 is configured as a master clock input (MCLK) 129210284Sjmallett 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN) 130210284Sjmallett 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2 131210284Sjmallett (PDMDIN1) 132210284Sjmallett 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4 133210284Sjmallett (PDMDIN2) 134210284Sjmallett 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6 135210284Sjmallett (PDMDIN3) 136210284Sjmallett 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8 137210284Sjmallett (PDMDIN4) 138210284Sjmallett 139210284Sjmallett output drive type for the GPIO pin can be one of the following: 140210284Sjmallett 0 - Hi-Z output 141210284Sjmallett 1 - Drive active low and active high 142210284Sjmallett 2 - (default) Drive active low and weak high 143210284Sjmallett 3 - Drive active low and Hi-Z 144210284Sjmallett 4 - Drive weak low and active high 145210284Sjmallett 5 - Drive Hi-Z and active high 146210284Sjmallett 147210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32-array 148210284Sjmallett minItems: 2 149210284Sjmallett maxItems: 2 150210284Sjmallett items: 151210284Sjmallett maximum: 15 152210284Sjmallett default: [2, 2] 153210284Sjmallett 154210284Sjmallett ti,asi-tx-drive: 155210284Sjmallett type: boolean 156210284Sjmallett description: | 157210284Sjmallett When set the device will set the Tx ASI output to a Hi-Z state for unused 158210284Sjmallett data cycles. Default is to drive the output low on unused ASI cycles. 159210284Sjmallett 160210284SjmallettpatternProperties: 161210284Sjmallett '^ti,gpo-config-[1-4]$': 162210284Sjmallett $ref: /schemas/types.yaml#/definitions/uint32-array 163210284Sjmallett description: | 164210284Sjmallett Defines the configuration and output driver for the general purpose 165210284Sjmallett output pins (GPO). These values are pairs, the first value is for the 166210284Sjmallett configuration type and the second value is for the output drive type. 167210284Sjmallett The array is defined as <GPO_CFG GPO_DRV> 168210284Sjmallett 169210284Sjmallett GPO output configuration can be one of the following: 170210284Sjmallett 171210284Sjmallett 0 - (default) disabled 172 1 - GPOX is configured as a general-purpose output (GPO) 173 2 - GPOX is configured as a device interrupt output (IRQ) 174 3 - GPOX is configured as a secondary ASI output (SDOUT2) 175 4 - GPOX is configured as a PDM clock output (PDMCLK) 176 177 GPO output drive configuration for the GPO pins can be one of the following: 178 179 0d - (default) Hi-Z output 180 1d - Drive active low and active high 181 2d - Drive active low and weak high 182 3d - Drive active low and Hi-Z 183 4d - Drive weak low and active high 184 5d - Drive Hi-Z and active high 185 186required: 187 - compatible 188 - reg 189 190additionalProperties: false 191 192examples: 193 - | 194 #include <dt-bindings/gpio/gpio.h> 195 i2c { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 codec: codec@4c { 199 compatible = "ti,tlv320adc5140"; 200 reg = <0x4c>; 201 ti,mic-bias-source = <6>; 202 ti,pdm-edge-select = <0 1 0 1>; 203 ti,gpi-config = <4 5 6 7>; 204 ti,gpio-config = <10 2>; 205 ti,gpo-config-1 = <0 0>; 206 ti,gpo-config-2 = <0 0>; 207 reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; 208 }; 209 }; 210