169990Sdes# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 269990Sdes%YAML 1.2 369990Sdes--- 469990Sdes$id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml# 569990Sdes$schema: http://devicetree.org/meta-schemas/core.yaml# 669990Sdes 769990Sdestitle: Cadence Sierra PHY 869990Sdes 969990Sdesdescription: 1069990Sdes This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink 1169990Sdes multiprotocol combinations including protocols such as PCIe, USB etc. 1269990Sdes 1369990Sdesmaintainers: 1469990Sdes - Swapnil Jakhade <sjakhade@cadence.com> 1569990Sdes - Yuti Amonkar <yamonkar@cadence.com> 1669990Sdes 1769990Sdesproperties: 1869990Sdes compatible: 1969990Sdes enum: 2069990Sdes - cdns,sierra-phy-t0 2169990Sdes - ti,sierra-phy-t0 2269990Sdes 2369990Sdes '#address-cells': 2469990Sdes const: 1 2569990Sdes 2669990Sdes '#size-cells': 2769990Sdes const: 0 2869990Sdes 2969990Sdes '#clock-cells': 3069990Sdes const: 1 3169990Sdes 3274840Sken resets: 3374840Sken minItems: 1 3484097Sdes items: 3569990Sdes - description: Sierra PHY reset. 3669990Sdes - description: Sierra APB reset. This is optional. 3769990Sdes 3884097Sdes reset-names: 3969990Sdes minItems: 1 4074840Sken items: 4184097Sdes - const: sierra_reset 4274840Sken - const: sierra_apb 4388950Skbyanc 4478340Sjlemon reg: 4588950Skbyanc maxItems: 1 4674840Sken description: 4769990Sdes Offset of the Sierra PHY configuration registers. 4884097Sdes 4984097Sdes reg-names: 5074840Sken const: serdes 5169990Sdes 5274840Sken clocks: 5374840Sken minItems: 2 5474840Sken maxItems: 4 5574840Sken 5674840Sken clock-names: 5774840Sken minItems: 2 5874840Sken items: 5974840Sken - const: cmn_refclk_dig_div 6069990Sdes - const: cmn_refclk1_dig_div 6171721Sdes - const: pll0_refclk 6271721Sdes - const: pll1_refclk 6371721Sdes 6471721Sdes cdns,autoconf: 6577989Sdes type: boolean 6671721Sdes description: 6771721Sdes A boolean property whose presence indicates that the PHY registers will be 6871721Sdes configured by hardware. If not present, all sub-node optional properties 6988950Skbyanc must be provided. 7088950Skbyanc 7171721SdespatternProperties: 7271721Sdes '^phy@[0-9a-f]$': 7371721Sdes type: object 7471721Sdes description: 7571721Sdes Each group of PHY lanes with a single master lane should be represented as 7671721Sdes a sub-node. Note that the actual configuration of each lane is determined 7771721Sdes by hardware strapping, and must match the configuration specified here. 7888950Skbyanc properties: 7988950Skbyanc reg: 8088950Skbyanc description: 8188950Skbyanc The master lane number. This is the lowest numbered lane in the lane group. 8271721Sdes minimum: 0 8371721Sdes maximum: 15 8471721Sdes 8574840Sken resets: 8669990Sdes minItems: 1 8773891Sdes maxItems: 4 8869990Sdes description: 8969990Sdes Contains list of resets, one per lane, to get all the link lanes out of reset. 9073891Sdes 9169990Sdes "#phy-cells": 9288950Skbyanc const: 0 9369990Sdes 9469990Sdes cdns,phy-type: 9569990Sdes description: 9669990Sdes Specifies the type of PHY for which the group of PHY lanes is used. 9769990Sdes Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. 9873891Sdes $ref: /schemas/types.yaml#/definitions/uint32 9969990Sdes enum: [2, 4] 10069990Sdes 10173891Sdes cdns,num-lanes: 10269990Sdes description: 10369990Sdes Number of lanes in this group. The group is made up of consecutive lanes. 10487594Sobrien $ref: /schemas/types.yaml#/definitions/uint32 10587594Sobrien minimum: 1 10674840Sken maximum: 16 10769990Sdes 10869990Sdes cdns,ssc-mode: 10974840Sken description: 11069990Sdes Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, 11188950Skbyanc EXTERNAL_SSC or INTERNAL_SSC. 11288950Skbyanc Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. 11388950Skbyanc $ref: /schemas/types.yaml#/definitions/uint32 11488950Skbyanc enum: [0, 1, 2] 11588950Skbyanc default: 1 11688950Skbyanc 11788950Skbyanc required: 11888950Skbyanc - reg 11988950Skbyanc - resets 12088950Skbyanc - "#phy-cells" 12188950Skbyanc 12288950Skbyanc additionalProperties: false 12388950Skbyanc 12488950Skbyancrequired: 12588950Skbyanc - compatible 12688950Skbyanc - "#address-cells" 12788950Skbyanc - "#size-cells" 12869990Sdes - reg 12988950Skbyanc - resets 13088950Skbyanc - reset-names 13188950Skbyanc 13288950SkbyancadditionalProperties: false 13388950Skbyanc 13488950Skbyancexamples: 13588950Skbyanc - | 13688950Skbyanc #include <dt-bindings/phy/phy.h> 13788950Skbyanc 13888950Skbyanc bus { 13988950Skbyanc #address-cells = <2>; 14088950Skbyanc #size-cells = <2>; 14188950Skbyanc 14288950Skbyanc sierra-phy@fd240000 { 14388950Skbyanc compatible = "cdns,sierra-phy-t0"; 14488950Skbyanc reg = <0x0 0xfd240000 0x0 0x40000>; 14588950Skbyanc resets = <&phyrst 0>, <&phyrst 1>; 14688950Skbyanc reset-names = "sierra_reset", "sierra_apb"; 14788950Skbyanc clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; 14888950Skbyanc clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 14988950Skbyanc #address-cells = <1>; 15088950Skbyanc #size-cells = <0>; 15188950Skbyanc pcie0_phy0: phy@0 { 15288950Skbyanc reg = <0>; 15388950Skbyanc resets = <&phyrst 2>; 15488950Skbyanc cdns,num-lanes = <2>; 15569990Sdes #phy-cells = <0>; 15669990Sdes cdns,phy-type = <PHY_TYPE_PCIE>; 15769990Sdes }; 15869990Sdes pcie0_phy1: phy@2 { 15977989Sdes reg = <2>; 16071721Sdes resets = <&phyrst 4>; 16169990Sdes cdns,num-lanes = <1>; 16271721Sdes #phy-cells = <0>; 16371721Sdes cdns,phy-type = <PHY_TYPE_PCIE>; 16488950Skbyanc }; 16588950Skbyanc }; 16669990Sdes }; 16788950Skbyanc