1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware Mobile Storage Host Controller
8
9maintainers:
10  - Ulf Hansson <ulf.hansson@linaro.org>
11  - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    enum:
19      - rockchip,rk3568-dwcmshc
20      - rockchip,rk3588-dwcmshc
21      - snps,dwcmshc-sdhci
22      - sophgo,cv1800b-dwcmshc
23      - sophgo,sg2002-dwcmshc
24      - thead,th1520-dwcmshc
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    minItems: 1
34    items:
35      - description: core clock
36      - description: bus clock for optional
37      - description: axi clock for rockchip specified
38      - description: block clock for rockchip specified
39      - description: timer clock for rockchip specified
40
41
42  clock-names:
43    minItems: 1
44    items:
45      - const: core
46      - const: bus
47      - const: axi
48      - const: block
49      - const: timer
50
51  resets:
52    maxItems: 5
53
54  reset-names:
55    items:
56      - const: core
57      - const: bus
58      - const: axi
59      - const: block
60      - const: timer
61
62  rockchip,txclk-tapnum:
63    description: Specify the number of delay for tx sampling.
64    $ref: /schemas/types.yaml#/definitions/uint8
65
66
67required:
68  - compatible
69  - reg
70  - interrupts
71  - clocks
72  - clock-names
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    mmc@fe310000 {
79      compatible = "rockchip,rk3568-dwcmshc";
80      reg = <0xfe310000 0x10000>;
81      interrupts = <0 25 0x4>;
82      clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
83      clock-names = "core", "bus", "axi", "block", "timer";
84      bus-width = <8>;
85      #address-cells = <1>;
86      #size-cells = <0>;
87    };
88  - |
89    mmc@aa0000 {
90      compatible = "snps,dwcmshc-sdhci";
91      reg = <0xaa000 0x1000>;
92      interrupts = <0 25 0x4>;
93      clocks = <&cru 17>, <&cru 18>;
94      clock-names = "core", "bus";
95      bus-width = <8>;
96      #address-cells = <1>;
97      #size-cells = <0>;
98    };
99
100...
101